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-rw-r--r--src/cpu/amd/car/cache_as_ram.inc20
-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c17
2 files changed, 18 insertions, 19 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index c773bd65bc..7cbf1dbcbb 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -17,6 +17,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
@@ -27,9 +28,6 @@
/* For CAR with Fam10h. */
#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
-#define MSR_MCFG_BASE 0xC0010058
-#define MSR_BU_CFG2 0xC001102A
-
#define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x
@@ -130,13 +128,13 @@ CAR_FAM10_out:
* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled.
*/
- movl $MSR_BU_CFG2, %ecx
+ movl $BU_CFG2_MSR, %ecx
rdmsr
bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */
wrmsr
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
- movl $MSR_BU_CFG2, %ecx
+ movl $BU_CFG2_MSR, %ecx
rdmsr
bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
wrmsr
@@ -171,7 +169,7 @@ CAR_FAM10_errata_applied:
#else
#error "bad MMCONF_BUS_NUMBER value"
#endif
- movl $MSR_MCFG_BASE, %ecx
+ movl $MMIO_CONF_BASE, %ecx
wrmsr
#endif
@@ -179,7 +177,7 @@ CAR_FAM10_out_post_errata:
/* Fam15h APIC IDs do not depend on NB config bit 54 */
jmp_if_not_fam15h(skip_nb54_set)
- movl $0xc001001f, %ecx /* NB_CFG_MSR */
+ movl $NB_CFG_MSR, %ecx
rdmsr
bts $(54 - 32), %edx /* Set NB config bit 54 */
wrmsr
@@ -227,7 +225,7 @@ skip_cu_check:
jmp_if_not_fam15h(CAR_FAM15_errata_applied)
/* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */
- movl $MSR_BU_CFG2, %ecx
+ movl $BU_CFG2_MSR, %ecx
rdmsr
bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */
wrmsr
@@ -410,7 +408,7 @@ fam10_mtrr_setup_complete:
post_code(0xa1)
/* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */
- mov $0xc0010015, %ecx
+ mov $HWCR_MSR, %ecx
rdmsr
btr $4, %eax
wrmsr
@@ -522,7 +520,7 @@ CAR_FAM10_ap:
* system with no obvious clues of what went wrong.
*
* So, need to get the NodeID and CoreID at first.
- * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
+ * If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need
* to reverse it.
*/
@@ -539,7 +537,7 @@ CAR_FAM10_ap:
shrl $24, %ebx
/* Get the nb cfg bit 54. */
- movl $0xc001001f, %ecx /* NB_CFG_MSR */
+ movl $NB_CFG_MSR, %ecx
rdmsr
movl %edi, %ecx /* CoreID bits */
bt $(54 - 32), %edx
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index a079ce49b1..5eda660775 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -21,6 +21,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
static __always_inline uint32_t amd_fam1x_cpu_family(void)
{
@@ -72,9 +73,9 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
}
/* INVDWBINVD = 1 */
- msr = rdmsr(0xc0010015);
+ msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 4);
- wrmsr(0xc0010015, msr);
+ wrmsr(HWCR_MSR, msr);
family = amd_fam1x_cpu_family();
@@ -83,15 +84,15 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
/* Family 15h or later */
/* DisSS = 0 */
- msr = rdmsr(0xc0011020);
+ msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(0x1 << 28);
- wrmsr(0xc0011020, msr);
+ wrmsr(LS_CFG_MSR, msr);
if (!skip_sharedc_config) {
/* DisSpecTlbRld = 0 */
- msr = rdmsr(0xc0011021);
+ msr = rdmsr(IC_CFG_MSR);
msr.lo &= ~(0x1 << 9);
- wrmsr(0xc0011021, msr);
+ wrmsr(IC_CFG_MSR, msr);
/* Erratum 714: SpecNbReqDis = 0 */
msr = rdmsr(BU_CFG2_MSR);
@@ -101,10 +102,10 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
/* DisSpecTlbRld = 0 */
/* DisHwPf = 0 */
- msr = rdmsr(0xc0011022);
+ msr = rdmsr(DC_CFG_MSR);
msr.lo &= ~(0x1 << 4);
msr.lo &= ~(0x1 << 13);
- wrmsr(0xc0011022, msr);
+ wrmsr(DC_CFG_MSR, msr);
}
#endif
}