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-rw-r--r--src/cpu/amd/model_fxx/Config.lb3
-rw-r--r--src/cpu/amd/model_fxx/fidvid.c78
-rw-r--r--src/cpu/amd/model_fxx/init_cpus.c107
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c154
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_update_microcode.c19
5 files changed, 335 insertions, 26 deletions
diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb
index ca83a1def1..0adfa28d08 100644
--- a/src/cpu/amd/model_fxx/Config.lb
+++ b/src/cpu/amd/model_fxx/Config.lb
@@ -1,7 +1,10 @@
uses HAVE_INIT_TIMER
uses HAVE_MOVNTI
+uses CPU_ADDR_BITS
+
default HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1
+default CPU_ADDR_BITS=40
dir /cpu/x86/tsc
dir /cpu/x86/fpu
dir /cpu/x86/mmx
diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index 8d1b84c24f..255a6828ed 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -4,6 +4,12 @@
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
+#ifndef SB_VFSMAF
+#define SB_VFSMAF 1
+#endif
+
+#define FX_SUPPORT 1
+
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
@@ -59,7 +65,7 @@ static void enable_fid_change(void)
dword |= (1<<14);// disable the DRAM interface at first, it will be enabled by raminit again
pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword);
- dword = 0x23070000; //enable FID/VID change
+ dword = 0x23070700; //enable FID/VID change
// dword = 0x00070000; //enable FID/VID change
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
@@ -122,13 +128,27 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if((vid_cur==vid) && (fid_cur==fid)) return fidvid;
vid_max = (msr.hi>>(48-32)) & 0x3f;
- fid_max = (msr.lo>>16) & 0x3f;
+ fid_max = ((msr.lo>>16) & 0x3f); //max fid
+#if FX_SUPPORT
+ if(fid_max>=((25-4)*2)) { // FX max fid is 5G
+ fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
+ if(fid_max >= ((25-4)*2)) {
+ fid_max = (10-4)*2; // hard set to 2G
+ }
+ }
+#endif
//set vid to max
msr.hi = 1;
msr.lo = (vid_max<<8) | (fid_cur);
+#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
+#endif
wrmsr(0xc0010041, msr);
+#if SB_VFSMAF == 0
+ ldtstop_sb();
+#endif
+
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
@@ -159,8 +179,13 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
//set target fid
msr.hi = (100000/5);
msr.lo = (vid_cur<<8) | fid_cur;
+#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
+#endif
wrmsr(0xc0010041, msr);
+#if SB_VFSMAF == 0
+ ldtstop_sb();
+#endif
#if K8_SET_FIDVID_DEBUG == 1
@@ -186,8 +211,13 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
//set vid to final
msr.hi = 1;
msr.lo = (vid<<8) | (fid_cur);
+#if SB_VFSMAF == 1
msr.lo |= (1<<16); // init changes
+#endif
wrmsr(0xc0010041, msr);
+#if SB_VFSMAF == 0
+ ldtstop_sb();
+#endif
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
@@ -215,10 +245,21 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
msr_t msr;
uint32_t vid_cur;
uint32_t fid_cur;
+ uint32_t fid_max;
int loop;
msr = rdmsr(0xc0010042);
- send = ((msr.lo>>16) & 0x3f) << 8; //max fid
+ fid_max = ((msr.lo>>16) & 0x3f); //max fid
+#if FX_SUPPORT
+ if(fid_max>=((25-4)*2)) { // FX max fid is 5G
+ fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
+ if(fid_max >= ((25-4)*2)) {
+ fid_max = (10-4)*2; // hard set to 2G
+ }
+ }
+#endif
+ send = fid_max<<8;
+
send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid
send |= (apicid<<24); // ap apicid
@@ -342,6 +383,14 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
msr_t msr;
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo>>16) & 0x3f); //max fid
+#if FX_SUPPORT == 1
+ if(fid_max>=((25-4)*2)) { // FX max fid is 5G
+ fid_max = ((msr.lo>>8) & 0x3f) + 5*2; // max FID is min fid + 1G
+ if(fid_max >= ((25-4)*2)) {
+ fid_max = (10-4)*2; // hard set to 2G
+ }
+ }
+#endif
vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max<<8)|(vid_max<<16);
@@ -366,6 +415,29 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
#endif
+#if 0
+ unsigned fid, vid;
+ // Can we use max only? So we can only set fid in one around, otherwise we need to set that to max after raminit
+ // set fid vid to DQS training required
+ fid = (fv.common_fidvid >> 8) & 0x3f;
+ vid = (fv.common_fidvid >> 16) & 0x3f;
+
+ if(fid>(10-4)*2) {
+ fid = (10-4)*2; //x10
+ }
+
+ if(vid>=0x1f) {
+ vid+= 4; //unit is 12.5mV
+ } else {
+ vid+= 2; //unit is 25mV
+ }
+
+ fv.common_fidvid = (fid<<8) | (vid<<16);
+
+ print_debug_fv("common_fidvid=", fv.common_fidvid);
+
+#endif
+
// set BSP fid and vid
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 50b1532f26..4e38a23be0 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -1,6 +1,12 @@
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID
- #define K8_SET_FIDVID 0
+ #if K8_REV_F_SUPPORT == 0
+ #define K8_SET_FIDVID 0
+ #else
+ // for rev F, need to set FID to max
+ #define K8_SET_FIDVID 1
+ #endif
+
#endif
#ifndef K8_SET_FIDVID_CORE0_ONLY
@@ -8,6 +14,43 @@
#define K8_SET_FIDVID_CORE0_ONLY 1
#endif
+static inline void print_initcpu8 (const char *strval, unsigned val)
+{
+#if CONFIG_USE_INIT
+ printk_debug("%s%02x\r\n", strval, val);
+#else
+ print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
+#endif
+}
+
+static inline void print_initcpu8_nocr (const char *strval, unsigned val)
+{
+#if CONFIG_USE_INIT
+ printk_debug("%s%02x", strval, val);
+#else
+ print_debug(strval); print_debug_hex8(val);
+#endif
+}
+
+
+static inline void print_initcpu16 (const char *strval, unsigned val)
+{
+#if CONFIG_USE_INIT
+ printk_debug("%s%04x\r\n", strval, val);
+#else
+ print_debug(strval); print_debug_hex16(val); print_debug("\r\n");
+#endif
+}
+
+static inline void print_initcpu(const char *strval, unsigned val)
+{
+#if CONFIG_USE_INIT
+ printk_debug("%s%08x\r\n", strval, val);
+#else
+ print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+#endif
+}
+
typedef void (*process_ap_t)(unsigned apicid, void *gp);
//core_range = 0 : all cores
@@ -44,7 +87,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
if(nb_cfg_54) {
if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation
- e0_later_single_core = is_e0_later_in_bsp(i); // single core
+ #if K8_REV_F_SUPPORT == 0
+ e0_later_single_core = is_e0_later_in_bsp(i); // single core
+ #else
+ e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
+ #endif
}
if(e0_later_single_core) {
j=1;
@@ -57,14 +104,17 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
if(core_range == 2) {
jstart = 1;
}
+ else {
+ jstart = 0;
+ }
if(e0_later_single_core || disable_siblings || (core_range==1)) {
jend = 0;
} else {
jend = siblings;
- }
-
-
+ }
+
+
for(j=jstart; j<=jend; j++) {
ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
@@ -141,10 +191,10 @@ static void wait_cpu_state(unsigned apicid, unsigned state)
if((readback & 0xff) == state) break; //target cpu is in stage started
}
}
-
static void wait_ap_started(unsigned ap_apicid, void *gp )
{
wait_cpu_state(ap_apicid, 0x33); // started
+ print_initcpu8_nocr(" ", ap_apicid);
}
static void wait_all_aps_started(unsigned bsp_apicid)
@@ -152,9 +202,11 @@ static void wait_all_aps_started(unsigned bsp_apicid)
for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
}
-static void wait_all_other_cores_started(unsigned bsp_apicid)
+static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0
{
+ print_debug("started ap apicid: ");
for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
+ print_debug("\r\n");
}
static void allow_all_aps_stop(unsigned bsp_apicid)
@@ -162,8 +214,23 @@ static void allow_all_aps_stop(unsigned bsp_apicid)
lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop
}
+static void STOP_CAR_AND_CPU(void)
+{
+ disable_cache_as_ram(); // inline
+ stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
+}
+#if RAMINIT_SYSINFO == 1
+
+#if MEM_TRAIN_SEQ != 1
+static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) {}
+#else
+static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
+#endif
+
+#endif
#if RAMINIT_SYSINFO == 1
+
static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo)
#else
static unsigned init_cpus(unsigned cpu_init_detectedx)
@@ -251,14 +318,16 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
init_fidvid_ap(bsp_apicid, apicid);
#endif
- // We need to stop the CACHE as RAM for this CPU, really?
- wait_cpu_state(bsp_apicid, 0x44);
- lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
+ // We need to stop the CACHE as RAM for this CPU, really?
+ wait_cpu_state(bsp_apicid, 0x44);
+ lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
+ set_init_ram_access();
+ #if RAMINIT_SYSINFO == 1
+ train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
+ #endif
- set_init_ram_access();
- disable_cache_as_ram(); // inline
- stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
- }
+ STOP_CAR_AND_CPU();
+ }
return bsp_apicid;
}
@@ -281,9 +350,13 @@ static void wait_all_core0_started(void)
unsigned i;
unsigned nodes = get_nodes();
- for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
- while(!is_core0_started(i)) {}
- }
+ print_debug("core0 started: ");
+ for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
+ while(!is_core0_started(i)) {}
+ print_initcpu8_nocr(" ", i);
+ }
+ print_debug("\r\n");
+
}
#endif
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 16d6509430..9e0ba84802 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -13,6 +13,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
+#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
@@ -29,6 +30,17 @@
#include <cpu/amd/model_fxx_msr.h>
+void cpus_ready_for_init(void)
+{
+#if MEM_TRAIN_SEQ == 1
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ // wait for ap memory to trained
+ wait_all_core0_mem_trained(sysinfox);
+#endif
+}
+
+
+#if K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@@ -53,6 +65,18 @@ int is_e0_later_in_bsp(int nodeid)
return e0_later;
}
+#endif
+
+#if K8_REV_F_SUPPORT == 1
+int is_cpu_f0_in_bsp(int nodeid)
+{
+ uint32_t dword;
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
+ dword = pci_read_config32(dev, 0xfc);
+ return (dword & 0xfff00) == 0x40f00;
+}
+#endif
#define MCI_STATUS 0x401
@@ -265,16 +289,20 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
-#if K8_HW_MEM_HOLE_SIZEK != 0
+#if HW_MEM_HOLE_SIZEK != 0
+ #if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
{
+ #endif
uint32_t val;
val = pci_read_config32(f1_dev, 0xf0);
if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10);
}
+ #if K8_REV_F_SUPPORT == 0
}
+ #endif
#endif
@@ -294,7 +322,7 @@ static void init_ecc_memory(unsigned node_id)
disable_lapic();
/* Walk through 2M chunks and zero them */
-#if K8_HW_MEM_HOLE_SIZEK != 0
+#if HW_MEM_HOLE_SIZEK != 0
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
for(basek = begink; basek < hole_startk;
@@ -336,9 +364,11 @@ static void init_ecc_memory(unsigned node_id)
printk_debug(" done\n");
}
+
static inline void k8_errata(void)
{
msr_t msr;
+#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
@@ -406,8 +436,11 @@ static inline void k8_errata(void)
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
+#endif
+#if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
+#endif
{
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
@@ -420,8 +453,95 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
+#if K8_REV_F_SUPPORT == 1
+ /* Erratum 131... */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.lo |= 1 << 20;
+ wrmsr(NB_CFG_MSR, msr);
+#endif
+
}
+#if K8_REV_F_SUPPORT == 1
+static void amd_set_name_string_f(device_t dev)
+{
+ unsigned socket;
+ unsigned cmpCap;
+ unsigned pwrLmt;
+ unsigned brandId;
+ unsigned brandTableIndex;
+ unsigned nN;
+ unsigned unknown = 1;
+
+ uint8_t str[48];
+ uint32_t *p;
+
+ msr_t msr;
+ unsigned i;
+
+ brandId = cpuid_ebx(0x80000001) & 0xffff;
+
+ printk_debug("brandId=%04x\n", brandId);
+ pwrLmt = ((brandId>>14) & 1) | ((brandId>>5) & 0x0e);
+ brandTableIndex = (brandId>>9) & 0x1f;
+ nN = (brandId & 0x3f) | ((brandId>>(15-6)) &(1<<6));
+
+ socket = (dev->device >> 4) & 0x3;
+
+ cmpCap = cpuid_ecx(0x80000008) & 0xff;
+
+
+ if((brandTableIndex == 0) && (pwrLmt == 0)) {
+ memset(str, 0, 48);
+ sprintf(str, "AMD Engineering Sample");
+ unknown = 0;
+ } else {
+
+ memset(str, 0, 48);
+ sprintf(str, "AMD Processor model unknown");
+
+ #if CPU_SOCKET_TYPE == 0x10
+ if(socket == 0x01) { // socket F
+ if ((cmpCap == 1) && ((brandTableIndex==0) ||(brandTableIndex ==1) ||(brandTableIndex == 4)) ) {
+ uint8_t pc[2];
+ unknown = 0;
+ switch (pwrLmt) {
+ case 2: pc[0]= 'E'; pc[1] = 'E'; break;
+ case 6: pc[0]= 'H'; pc[1] = 'E'; break;
+ case 0xa: pc[0]= ' '; pc[1] = ' '; break;
+ case 0xc: pc[0]= 'S'; pc[1] = 'E'; break;
+ default: unknown = 1;
+
+ }
+ if(!unknown) {
+ memset(str, 0, 48);
+ sprintf(str, "Dual-Core AMD Opteron(tm) Processor %1d2%2d %c%c", brandTableIndex<<1, (nN-1)&0x3f, pc[0], pc[1]);
+ }
+ }
+ }
+ #else
+ #if CPU_SOCKET_TYPE == 0x11
+ if(socket == 0x00) { // socket AM2
+ if(cmpCap == 0) {
+ sprintf(str, "Athlon 64");
+ } else {
+ sprintf(str, "Athlon 64 Dual Core");
+ }
+
+ }
+ #endif
+ #endif
+ }
+
+ p = str;
+ for(i=0;i<6;i++) {
+ msr.lo = *p; p++; msr.hi = *p; p++;
+ wrmsr(0xc0010030+i, msr);
+ }
+
+
+}
+#endif
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
int init_processor_name(void);
@@ -435,6 +555,16 @@ void model_fxx_init(device_t dev)
unsigned siblings;
#endif
+#if K8_REV_F_SUPPORT == 1
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, dev->device);
+
+ if((c.x86_model & 0xf0) == 0x40) {
+ amd_set_name_string_f(dev);
+ }
+#endif
+
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
@@ -504,6 +634,7 @@ static struct device_operations cpu_dev_ops = {
.init = model_fxx_init,
};
static struct cpu_device_id cpu_table[] = {
+#if K8_REV_F_SUPPORT == 0
{ X86_VENDOR_AMD, 0xf50 }, /* B3 */
{ X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
{ X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
@@ -540,6 +671,25 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x20fc2 },
{ X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
{ X86_VENDOR_AMD, 0x20f32 },
+#endif
+
+#if K8_REV_F_SUPPORT == 1
+//AMD_F0_SUPPORT
+ { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */
+ { X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */
+ { X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */
+ { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */
+ { X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */
+ { X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */
+ { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */
+ { X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
+ { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */
+ { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */
+ { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */
+ { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */
+ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */
+ { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
+#endif
{ 0, 0 },
};
diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
index 63820f5bed..e210846479 100644
--- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
+++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
@@ -1,5 +1,5 @@
/* Copyright 2005 AMD
- * 2005.08 yhlu add microcode support
+ * 2005.08 yhlu add microcode support
*/
/*============================================================================
Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
@@ -52,10 +52,15 @@ $1.0$
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
-#include "microcode_rev_c.h"
-#include "microcode_rev_d.h"
-#include "microcode_rev_e.h"
+#if K8_REV_F_SUPPORT == 0
+ #include "microcode_rev_c.h"
+ #include "microcode_rev_d.h"
+ #include "microcode_rev_e.h"
+#endif
+#if K8_REV_F_SUPPORT == 1
+// #include "microcode_rev_f.h"
+#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@@ -65,6 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = {
+ #if K8_REV_F_SUPPORT == 0
0x0f48, 0x0048,
0x0f58, 0x0048,
@@ -85,6 +91,11 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20f12, 0x0210,
0x20f32, 0x0210,
0x20fb1, 0x0210,
+ #endif
+
+ #if K8_REV_F_SUPPORT == 1
+
+ #endif
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 22:44:46 +0000