diff options
Diffstat (limited to 'src/cpu/amd/model_lx/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/model_lx/cache_as_ram.inc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index a2e8f87e64..a1d775d6d6 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -26,6 +26,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include <cpu/amd/lxdef.h> +#include <cpu/x86/post_code.h> /*************************************************************************** /** /** DCacheSetup @@ -210,7 +211,7 @@ done_cache_as_ram_main: /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +228,7 @@ __main: call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt |