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-rw-r--r--src/cpu/amd/mtrr/amd_earlymtrr.c1
-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c4
2 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c
index f2de79102b..948d4ac83b 100644
--- a/src/cpu/amd/mtrr/amd_earlymtrr.c
+++ b/src/cpu/amd/mtrr/amd_earlymtrr.c
@@ -15,7 +15,6 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
*/
msr_t msr;
const unsigned long *msr_addr;
- unsigned long cr0;
#if 0
/* Enable the access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index b422f9f425..e8e9273868 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -149,7 +149,7 @@ void amd_setup_mtrrs(void)
msr.lo = state.mmio_basek << 10;
wrmsr(TOP_MEM, msr);
- if(state.tomk>(4*1024*1024)) {
+ if(state.tomk > (4*1024*1024)) {
/* Setup TOP_MEM2 */
msr.hi = state.tomk >> 22;
msr.lo = state.tomk << 10;
@@ -180,7 +180,7 @@ void amd_setup_mtrrs(void)
/* FIXME we should probably query the cpu for this
* but so far this is all any recent AMD cpu has supported.
*/
- address_bits = 40;
+ address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
/* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory.