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Diffstat (limited to 'src/cpu/amd/pi/Kconfig')
| -rw-r--r-- | src/cpu/amd/pi/Kconfig | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig new file mode 100644 index 0000000000..366beb41c1 --- /dev/null +++ b/src/cpu/amd/pi/Kconfig @@ -0,0 +1,76 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_PI + bool + default y if CPU_AMD_PI_00730F01 + default n + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER + select BROKEN_CAR_MIGRATE + select SPI_FLASH if HAVE_ACPI_RESUME + +if CPU_AMD_PI + +config UDELAY_IO + bool + default n + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD platforms, one socket supports 2 or more kinds of + processor family, compiling several CPU families agesa code + will increase the romstage size. + In order to execute romstage in place on the flash ROM, + more space is required to be set as write through caching. + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in PI vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config S3_DATA_POS + hex + default 0xFFFF0000 + +config S3_DATA_SIZE + int + default 32768 + +endif # CPU_AMD_PI + +source src/cpu/amd/pi/00730F01/Kconfig |