diff options
Diffstat (limited to 'src/cpu/amd/pi')
| -rw-r--r-- | src/cpu/amd/pi/00630F01/model_15_init.c | 5 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00660F01/model_15_init.c | 5 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00730F01/model_16_init.c | 5 |
3 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 592ca4f086..0269a1e260 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -35,6 +35,7 @@ static void model_15_init(struct device *dev) u8 i; msr_t msr; + int num_banks; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) @@ -69,9 +70,11 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 0540a72fad..424a6c06ff 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -51,6 +51,7 @@ static void model_15_init(struct device *dev) u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -81,9 +82,11 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 3ae841d0b1..1f2c30fd03 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -34,6 +34,7 @@ static void model_16_init(struct device *dev) u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -66,9 +67,11 @@ static void model_16_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ |