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-rw-r--r--src/cpu/amd/pi/00630F01/Kconfig4
-rw-r--r--src/cpu/amd/pi/00660F01/Kconfig4
-rw-r--r--src/cpu/amd/pi/00730F01/Kconfig4
-rw-r--r--src/cpu/amd/pi/Kconfig12
4 files changed, 1 insertions, 23 deletions
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
index e5e27b55b4..37025ab4bf 100644
--- a/src/cpu/amd/pi/00630F01/Kconfig
+++ b/src/cpu/amd/pi/00630F01/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int
default 48
-config XIP_ROM_SIZE
- hex
- default 0x100000
-
endif
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
index 647044843a..374672da03 100644
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ b/src/cpu/amd/pi/00660F01/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int
default 48
-config XIP_ROM_SIZE
- hex
- default 0x100000
-
endif
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index 43abc80aba..7ba49439eb 100644
--- a/src/cpu/amd/pi/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -23,8 +23,4 @@ config CPU_ADDR_BITS
int
default 40
-config XIP_ROM_SIZE
- hex
- default 0x100000
-
endif
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 973a086e9f..b33302ecef 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -28,23 +28,13 @@ config CPU_AMD_PI
select SPI_FLASH if HAVE_ACPI_RESUME
select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
select SMM_ASEG
+ select NO_FIXED_XIP_ROM_SIZE
if CPU_AMD_PI
config BINARYPI_LEGACY_WRAPPER
def_bool n
-config XIP_ROM_SIZE
- hex
- default 0x100000
- help
- Overwride the default write through caching size as 1M Bytes.
- On some AMD platforms, one socket supports 2 or more kinds of
- processor family, compiling several CPU families agesa code
- will increase the romstage size.
- In order to execute romstage in place on the flash ROM,
- more space is required to be set as write through caching.
-
config UDELAY_LAPIC_FIXED_FSB
int
default 200