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-rw-r--r--src/cpu/amd/agesa/family12/model_12_init.c4
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c4
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c6
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c4
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc4
-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c2
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/cpu/amd/family_10h-family_15h/fidvid.c18
-rw-r--r--src/cpu/amd/family_10h-family_15h/init_cpus.c40
-rw-r--r--src/cpu/amd/family_10h-family_15h/model_10xxx_init.c6
-rw-r--r--src/cpu/amd/family_10h-family_15h/powernow_acpi.c2
-rw-r--r--src/cpu/amd/family_10h-family_15h/ram_calc.c2
-rw-r--r--src/cpu/amd/microcode/microcode.c6
-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c2
-rw-r--r--src/cpu/amd/pi/00630F01/model_15_init.c6
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c2
-rw-r--r--src/cpu/amd/pi/00660F01/model_15_init.c4
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c2
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c4
-rw-r--r--src/cpu/amd/quadcore/quadcore.c4
20 files changed, 62 insertions, 62 deletions
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 96d6cdc637..0693dedeb8 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -34,7 +34,7 @@ static void model_12_init(struct device *dev)
msr_t msr;
int num_banks;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -65,7 +65,7 @@ static void model_12_init(struct device *dev)
/* Set the processor name string */
// init_processor_name();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 3086f158df..1516a6b2c6 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -33,7 +33,7 @@ static void model_14_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
@@ -83,7 +83,7 @@ static void model_14_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 7528431e07..26b20dcfd4 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -37,7 +37,7 @@ static void model_15_init(struct device *dev)
int num_banks;
int msrno;
unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -82,7 +82,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -102,7 +102,7 @@ static void model_15_init(struct device *dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 188f95cf08..e6fb0db6de 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -35,7 +35,7 @@ static void model_16_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -80,7 +80,7 @@ static void model_16_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index e4c2704727..f923a47db4 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -141,7 +141,7 @@ CAR_FAM10_out:
CAR_FAM10_errata_applied:
-#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+#if CONFIG(MMCONF_SUPPORT)
#if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
#error "MMCONF_BASE_ADDRESS too big"
#elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
@@ -315,7 +315,7 @@ clear_fixed_var_mtrr_out:
*/
.endm
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
#if CacheSize > 0x80000
#error Invalid CAR size, must be at most 128k (processor limit is 512k).
#endif
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index b1d0c5a1e1..199a453501 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -80,7 +80,7 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
family = amd_fam1x_cpu_family();
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
if (family >= 0x6f) {
/* Family 15h or later */
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index e55ef408f3..18e7542e6d 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -36,7 +36,7 @@
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
-#if IS_ENABLED(CONFIG_DEBUG_CAR)
+#if CONFIG(DEBUG_CAR)
#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
#else
#define print_car_debug(format, arg...)
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 428924df34..db58f5dd34 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -95,21 +95,21 @@ b.- prep_fid_change(...)
static inline void print_debug_fv(const char *str, u32 val)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, u8 val)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
@@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
}
/* TODO: look into C1E state and F3xA0[IdleExitEn]*/
- #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+ #if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & AMD_FAM10_C3) {
dword |= SVI_HIGH_FREQ_ON;
}
@@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
if (cpuRev & AMD_DR_Bx ) {
smaf001 = 0xA6;
} else {
- #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+ #if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
smaf001 = 0xF6;
}
@@ -1036,7 +1036,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid)
}
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st {
u32 num;
// it could use 256 bytes for 64 node quad core system
@@ -1055,7 +1055,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st ap_apicidx;
u32 i;
#endif
@@ -1070,8 +1070,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
print_debug_fv("BSP fid = ", fv.common_fid);
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
- !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
+ !CONFIG(SET_FIDVID_CORE0_ONLY)
/* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 57d4424bb1..76bc6d99e5 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -18,7 +18,7 @@
#include <device/pci_ops.h>
#include "init_cpus.h"
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
#include <pc80/mc146818rtc.h>
@@ -30,17 +30,17 @@
#include <southbridge/amd/common/reset.h>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700)
#include <southbridge/amd/sb700/sb700.h>
#endif
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB800)
#include <southbridge/amd/sb800/sb800.h>
#endif
#include "cpu/amd/car/disable_cache_as_ram.c"
-#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
+#if CONFIG(PCI_IO_CFG_EXT)
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG_MSR[46]=1;
@@ -156,7 +156,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
/* get_nodes define in ht_wrapper.c */
nodes = get_nodes();
- if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
+ if (!CONFIG(LOGICAL_CPUS) ||
read_option(multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1;
} else {
@@ -186,8 +186,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
for (j = jstart; j <= jend; j++) {
ap_apicid = get_boot_apic_id(i, j);
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if !CONFIG(LIFT_BSP_APIC_ID)
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
return result;
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
#endif
@@ -402,17 +402,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
if (!is_fam15h())
set_apicid_cpuid_lo();
set_EnableCf8ExtCfg();
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID)
enable_apic_ext_id(id.nodeid);
#endif
}
enable_lapic();
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if !CONFIG(LIFT_BSP_APIC_ID)
if (initial_apicid != 0) // other than bsp
#endif
{
@@ -424,7 +424,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
lapic_write(LAPIC_ID, dword);
}
-#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(LIFT_BSP_APIC_ID)
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
@@ -477,8 +477,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
}
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID)
+#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY)
// Run on all AP for proper FID/VID setup.
if (id.coreid == 0) // only need set fid for core0
#endif
@@ -501,7 +501,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
if (is_fam15h()) {
/* core 1 on node 0 is special; to avoid corrupting the
* BSP do not alter MTRRs on that core */
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1;
else
fam15_bsp_core1_apicid = 1;
@@ -578,7 +578,7 @@ static void start_node(u8 node)
/* Enable routing table */
printk(BIOS_DEBUG, "Start node %02x", node);
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
+#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/* For FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3);
@@ -1040,7 +1040,7 @@ void cpuSetAMDMSR(uint8_t node_id)
}
}
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(MSR_INTPEND);
@@ -1060,7 +1060,7 @@ void cpuSetAMDMSR(uint8_t node_id)
if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
enable_c_states = 0;
- if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+ if (CONFIG(HAVE_ACPI_TABLES))
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
@@ -1869,7 +1869,7 @@ void finalize_node_setup(struct sys_info *sysinfo)
cpuSetAMDPCI(i);
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
// Prep each node for FID/VID setup.
prep_fid_change();
#endif
@@ -1883,6 +1883,6 @@ void finalize_node_setup(struct sys_info *sysinfo)
#endif
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
# include "fidvid.c"
#endif
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 674ba782d7..9819caf909 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -62,7 +62,7 @@ static void model_10xxx_init(struct device *dev)
msr_t msr;
int num_banks;
struct node_core_id id;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
uint8_t delay_start;
@@ -123,7 +123,7 @@ static void model_10xxx_init(struct device *dev)
/* Set the processor name string */
init_processor_name();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -204,7 +204,7 @@ static void model_10xxx_init(struct device *dev)
wrmsr(BU_CFG2_MSR, msr);
}
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
/* Set SMM base address for this CPU */
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
index 15b655028c..d024069e30 100644
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
@@ -187,7 +187,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
uint8_t enable_c_states;
enable_c_states = 0;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
#endif
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 344dc77d07..1433e0753f 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -44,7 +44,7 @@ static inline uint8_t is_fam15h(void)
uint64_t get_uma_memory_size(uint64_t topmem)
{
uint64_t uma_size = 0;
- if (IS_ENABLED(CONFIG_GFXUMA)) {
+ if (CONFIG(GFXUMA)) {
/* refer to UMA Size Consideration in 780 BDG. */
if (topmem >= 0x40000000) /* 1GB and above system memory */
uma_size = 0x10000000; /* 256M recommended UMA */
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 783675d953..584041e923 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -200,7 +200,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
}
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif
@@ -210,7 +210,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
@@ -220,7 +220,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index ae2a2dfe88..10fd9f568c 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -88,7 +88,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ if (CONFIG(UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 5455b0cf11..3a641bf07f 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -36,7 +36,7 @@ static void model_15_init(struct device *dev)
int num_banks;
int msrno;
unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -78,7 +78,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -98,7 +98,7 @@ static void model_15_init(struct device *dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index e028b6f85b..2cbeab8316 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -94,7 +94,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+ if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index d156525b60..65d87c22ec 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -51,7 +51,7 @@ static void model_15_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -90,7 +90,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 163066b6d8..3769319866 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -99,7 +99,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+ if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 7ae89b48e8..5678c5f58d 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -34,7 +34,7 @@ static void model_16_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -75,7 +75,7 @@ static void model_16_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 601675123e..ad4a7ead6d 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
@@ -124,7 +124,7 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
}
}
-#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+#if (!CONFIG(CPU_AMD_MODEL_10XXX))
//it is running on core0 of node0
static void start_other_cores(void)
{