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-rw-r--r--src/cpu/amd/dualcore/Makefile.inc2
-rw-r--r--src/cpu/amd/dualcore/amd_sibling.c20
-rw-r--r--src/cpu/amd/dualcore/dualcore_id.c8
-rw-r--r--src/cpu/amd/model_10xxx/Makefile.inc2
-rw-r--r--src/cpu/amd/model_10xxx/mc_patch_01000095.h2
-rw-r--r--src/cpu/amd/model_10xxx/model_10xxx_init.c12
-rw-r--r--src/cpu/amd/model_fxx/Makefile.inc2
-rw-r--r--src/cpu/amd/model_fxx/apic_timer.c2
-rw-r--r--src/cpu/amd/model_fxx/fidvid.c4
-rw-r--r--src/cpu/amd/model_fxx/microcode_rev_c.h2
-rw-r--r--src/cpu/amd/model_fxx/microcode_rev_d.h2
-rw-r--r--src/cpu/amd/model_fxx/microcode_rev_e.h2
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_update_microcode.c6
-rw-r--r--src/cpu/amd/model_fxx/processor_name.c16
-rw-r--r--src/cpu/amd/model_gx2/cpubug.c42
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c28
-rw-r--r--src/cpu/amd/model_lx/cpubug.c6
-rw-r--r--src/cpu/amd/model_lx/cpureginit.c4
-rw-r--r--src/cpu/amd/model_lx/msrinit.c6
-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c8
-rw-r--r--src/cpu/amd/sc520/raminit.c100
-rw-r--r--src/cpu/amd/sc520/sc520.c20
22 files changed, 148 insertions, 148 deletions
diff --git a/src/cpu/amd/dualcore/Makefile.inc b/src/cpu/amd/dualcore/Makefile.inc
index ee2d93c928..8b6d688300 100644
--- a/src/cpu/amd/dualcore/Makefile.inc
+++ b/src/cpu/amd/dualcore/Makefile.inc
@@ -1,2 +1,2 @@
-# This is a leaf Makefile, no conditionals. If it is included it will be used.
+# This is a leaf Makefile, no conditionals. If it is included it will be used.
obj-y += amd_sibling.o
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 28a813c6a5..af96265d6c 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -27,12 +27,12 @@ static int get_max_siblings(int nodes)
for(nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
- j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
+ j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if(siblings < j) {
siblings = j;
}
}
-
+
return siblings;
}
@@ -47,7 +47,7 @@ static void enable_apic_ext_id(int nodes)
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
val |= (1<<17)|(1<<18);
- pci_write_config32(dev, 0x68, val);
+ pci_write_config32(dev, 0x68, val);
}
}
@@ -70,9 +70,9 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
if(bsp_apic_id > 0) { // io apic could start from 0
- return 0;
+ return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
- return 1;
+ return 1;
}
nb_cfg_54 = read_nb_cfg_54();
@@ -100,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
- apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
+ apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
}
else {
@@ -112,7 +112,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
-
+
return apicid_base;
}
@@ -145,7 +145,7 @@ void amd_sibling_init(device_t cpu)
siblings);
#endif
- nb_cfg_54 = read_nb_cfg_54();
+ nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
@@ -159,7 +159,7 @@ void amd_sibling_init(device_t cpu)
return;
}
#endif
-
+
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
@@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu)
new->path.apic.core_id = i;
#if 1
- printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
+ printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index a2b180b2b6..9a1a9c53d4 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void)
return ( ( msr.hi >> (54-32)) & 1);
}
-static inline unsigned get_initial_apicid(void)
+static inline unsigned get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xf);
}
@@ -22,7 +22,7 @@ static inline unsigned get_initial_apicid(void)
//called by amd_siblings too
#define CORE_ID_BIT 1
#define NODE_ID_BIT 3
-struct node_core_id get_node_core_id(unsigned nb_cfg_54)
+struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
@@ -31,8 +31,8 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>CORE_ID_BIT);
id.coreid &= ((1<<CORE_ID_BIT)-1);
- }
- else
+ }
+ else
{
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index d0beb04c98..db3debce2e 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -1,4 +1,4 @@
-# no conditionals here. If you include this file from a socket, then you get all the binaries.
+# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_10xxx_init.o
obj-y += update_microcode.o
obj-y += apic_timer.o
diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000095.h b/src/cpu/amd/model_10xxx/mc_patch_01000095.h
index 1227f310f1..bfb2e107f7 100644
--- a/src/cpu/amd/model_10xxx/mc_patch_01000095.h
+++ b/src/cpu/amd/model_10xxx/mc_patch_01000095.h
@@ -112,7 +112,7 @@
0x0f, 0xe0, 0xdf, 0xf0, 0x23, 0x03, 0x00, 0x8e, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
-
+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 5a19547b4d..992c957913 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -134,12 +134,12 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100f22 },
{ X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
- { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
- { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
- { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
- { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
- { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
- { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
+ { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
+ { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
+ { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
+ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
+ { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
+ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 },
};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index ea3088b46a..d7490e8fa9 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -1,4 +1,4 @@
-# no conditionals here. If you include this file from a socket, then you get all the binaries.
+# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_fxx_init.o
obj-y += apic_timer.o
obj-y += model_fxx_update_microcode.o
diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c
index 8eeb32fee9..6eb99a4eba 100644
--- a/src/cpu/amd/model_fxx/apic_timer.c
+++ b/src/cpu/amd/model_fxx/apic_timer.c
@@ -25,5 +25,5 @@ void udelay(unsigned usecs)
do {
value = lapic_read(LAPIC_TMCCT);
} while((start - value) < ticks);
-
+
}
diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c
index edc7ac909c..bfbc93d577 100644
--- a/src/cpu/amd/model_fxx/fidvid.c
+++ b/src/cpu/amd/model_fxx/fidvid.c
@@ -424,7 +424,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{
- /* FIXME: need to check the change path to verify if it is reachable
+ /* FIXME: need to check the change path to verify if it is reachable
* when common fid is small than 1.6G */
if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
return fidvid;
@@ -549,7 +549,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* let all ap trains to state 1 */
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
- /* calculate the common max fid/vid that could be used for
+ /* calculate the common max fid/vid that could be used for
* all APs and BSP */
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0;
diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h
index f102d37d0f..980572439f 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_c.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_c.h
@@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_fxx/microcode_rev_d.h b/src/cpu/amd/model_fxx/microcode_rev_d.h
index 7fc0666de6..61a510c2b2 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_d.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_d.h
@@ -94,7 +94,7 @@
0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_fxx/microcode_rev_e.h b/src/cpu/amd/model_fxx/microcode_rev_e.h
index 8d9a5813d4..7cdeed0016 100644
--- a/src/cpu/amd/model_fxx/microcode_rev_e.h
+++ b/src/cpu/amd/model_fxx/microcode_rev_e.h
@@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
index 68a2cea070..976168102b 100644
--- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
+++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
@@ -94,7 +94,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
-
+
#endif
};
@@ -102,7 +102,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
unsigned new_id;
int i;
-
+
new_id = 0;
for(i=0; i<sizeof(id_mapping_table); i+=2 ) {
@@ -112,7 +112,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
}
}
- return new_id;
+ return new_id;
}
diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c
index 4d86467632..8465e3ce34 100644
--- a/src/cpu/amd/model_fxx/processor_name.c
+++ b/src/cpu/amd/model_fxx/processor_name.c
@@ -77,7 +77,7 @@ static const char *processor_names[]={
/* 0x24 */ "AMD Athlon(tm) 64 FX-ZZ Processor",
/* 0x25 */ NULL,
/* 0x26 */ "AMD Sempron(tm) Processor TT00+",
- /* 0x27-0x28 */ NULL, NULL,
+ /* 0x27-0x28 */ NULL, NULL,
/* 0x29 */ "Dual Core AMD Opteron(tm) Processor 1RR SE",
/* 0x2A */ "Dual Core AMD Opteron(tm) Processor 2RR SE",
/* 0x2B */ "Dual Core AMD Opteron(tm) Processor 8RR SE",
@@ -404,13 +404,13 @@ int init_processor_name(void)
memset(program_string, 0, 48);
strcpy(program_string, processor_name_string);
-
+
/* Now create a model number - See Table 4. Model Number Calculation
- * in the Revision Guide. NOTE: #6, EE was changed to VV because
+ * in the Revision Guide. NOTE: #6, EE was changed to VV because
* otherwise it clashes with the brand names.
*/
-
- for (i=0; i<47; i++) { // 48 -1
+
+ for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if CONFIG_K8_REV_F_SUPPORT == 0
@@ -430,11 +430,11 @@ int init_processor_name(void)
case 'Y': ModelNumber = 29 + NN; break;
#endif
}
-
+
if(ModelNumber && ModelNumber < 100) {
// No idea what to do with RR=100. According
// to the revision guide this is possible.
- //
+ //
// --> "AMD Opteron(tm) Processor 8100"?
program_string[i]=(ModelNumber/10)+'0';
program_string[i+1]=(ModelNumber%10)+'0';
@@ -442,7 +442,7 @@ int init_processor_name(void)
}
}
}
-
+
printk(BIOS_DEBUG, "CPU model %s\n", program_string);
for (i=0; i<6; i++) {
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index 82570f5b0a..f900661959 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -50,8 +50,8 @@ pcideadlock(void)
msr_t msr;
/*
- * forces serialization of all load misses. Setting this bit prevents the
- * DM pipe from backing up if a read request has to be held up waiting
+ * forces serialization of all load misses. Setting this bit prevents the
+ * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
@@ -61,14 +61,14 @@ pcideadlock(void)
wrmsr(CPU_DM_CONFIG0, msr);
/* interlock instruction fetches to WS regions with data accesses.
- * This prevents an instruction fetch from going out to PCI if the
+ * This prevents an instruction fetch from going out to PCI if the
* data side is about to make a request.
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
-
- /* write serialize memory hole to PCI. Need to unWS when something is
+
+ /* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
@@ -78,7 +78,7 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
-/****************************************************************************
+/****************************************************************************
*
* CPUbug784
*
@@ -176,7 +176,7 @@ eng2900(void)
wrmsr(0x3003, msr);
/* change this value to zero if you need to disable this BTB SWAPSiF. */
- if (1) {
+ if (1) {
/* Disable enable_actions in DIAGCTL while setting up GLCP */
msr.hi = 0;
@@ -192,16 +192,16 @@ eng2900(void)
msr.lo = 2;
wrmsr(MSR_GLCP + 0x0016, msr);
- /* The code below sets up the CPU to stall for 4 GeodeLink
- * clocks when CPU is snooped. Because setting XSTATE to 0
- * overrides any other XSTATE action, the code will always
- * stall for 4 GeodeLink clocks after a snoop request goes
- * away even if it occured a clock or two later than a
- * different snoop; the stall signal will never 'glitch high'
+ /* The code below sets up the CPU to stall for 4 GeodeLink
+ * clocks when CPU is snooped. Because setting XSTATE to 0
+ * overrides any other XSTATE action, the code will always
+ * stall for 4 GeodeLink clocks after a snoop request goes
+ * away even if it occured a clock or two later than a
+ * different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
- /* Send mb0 port 3 requests to upper GeodeLink diag bits
+ /* Send mb0 port 3 requests to upper GeodeLink diag bits
[63:32] */
msr.hi = 0;
msr.lo = 0x80338041;
@@ -222,25 +222,25 @@ eng2900(void)
msr.lo = 0;
wrmsr(MSR_GLCP + 0x004D, msr);
- /* Writing action number 13: XSTATE=0 to occur when CPU is
+ /* Writing action number 13: XSTATE=0 to occur when CPU is
snooped unless we're stalled */
msr.hi = 0;
msr.lo = 0x00400000;
wrmsr(MSR_GLCP + 0x0075, msr);
- /* Writing action number 11: inc XSTATE every GeodeLink clock
+ /* Writing action number 11: inc XSTATE every GeodeLink clock
unless we're idle */
msr.hi = 0;
msr.lo = 0x30000;
wrmsr(MSR_GLCP + 0x0073, msr);
- /* Writing action number 5: STALL_CPU_PIPE when exitting idle
+ /* Writing action number 5: STALL_CPU_PIPE when exitting idle
state or not in idle state */
msr.hi = 0;
msr.lo = 0x00430000;
wrmsr(MSR_GLCP + 0x006D, msr);
- /* Writing DIAGCTL Register to enable the stall action and to
+ /* Writing DIAGCTL Register to enable the stall action and to
let set5m watch the upper GeodeLink diag bits. */
msr.hi = 0;
msr.lo = 0x80004000;
@@ -338,7 +338,7 @@ static void bug118339(void)
/***/
/****************************************************************************/
static void disablememoryreadorder(void)
-{
+{
msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
@@ -365,7 +365,7 @@ cpubug(void)
case 0x20:
pcideadlock();
eng1398();
- /* cs 5530 bug; ignore
+ /* cs 5530 bug; ignore
bug752();
*/
break;
@@ -376,7 +376,7 @@ cpubug(void)
bug118339();
break;
case 0x22:
- case 0x30:
+ case 0x30:
break;
default:
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index 5e786910c5..3cb3cf1a58 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -18,7 +18,7 @@ BIST(void){
msr = rdmsr(msrnum);
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
wrmsr(msrnum, msr);
-
+
msr.lo = 0x00000003F;
msr.hi = 0x000000000;
msrnum = CPU_DM_BIST;
@@ -29,7 +29,7 @@ BIST(void){
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
-
+
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
@@ -89,58 +89,58 @@ cpuRegInit (void){
msr.hi = 0;
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
wrmsr(msrnum, msr);
-
+
/* Set up GLCP to grab BTM data.*/
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
-
+
/* ;Turn off debug clock*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x00; /* No clock*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
-
+
/* ;Set debug clock to CPU*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x01; /* CPU CLOCK*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
-
+
/* ;Set fifo ctl to BTM bits wide*/
msrnum = 0x04C00005E; /* FIFO_CTL*/
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
/* Bit [19] sets it up in slow data mode.*/
-
+
/* ;enable fifo loading - BTM sizing will constrain*/
/* ; only valid BTM packets to load - this action should always be on*/
-
+
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
msr.hi = 0x000000000; /* */
wrmsr(msrnum, msr);
-
+
/* ;start storing diag data in the fifo*/
msrnum = 0x04C00005F; /* DIAG CTL*/
msr.lo = 0x080000000; /* enable actions*/
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
-
+
/* Set up delay on data lines, so that the hold time*/
/* is 1 ns.*/
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
wrmsr(msrnum, msr);
-
+
/* Set up DF to output diag information on DF pins.*/
msrnum = DF_GLD_MSR_MASTER_CONF;
msr.lo = 0x0220;
msr.hi = 0;
wrmsr(msrnum, msr);
-
+
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
@@ -237,7 +237,7 @@ cpuRegInit (void){
/* */
/* This code disables the data cache. Don't execute this
* unless you're testing something.
- */
+ */
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@@ -249,7 +249,7 @@ cpuRegInit (void){
}
/* This code disables the instruction cache. Don't execute
* this unless you're testing something.
- */
+ */
/* Allow NVRam to override IM Setup*/
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
{
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
index 203d63b81e..e3b6e511ee 100644
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -44,15 +44,15 @@ static void pcideadlock(void)
msr_t msr;
/*
- * forces serialization of all load misses. Setting this bit prevents the
- * DM pipe from backing up if a read request has to be held up waiting
+ * forces serialization of all load misses. Setting this bit prevents the
+ * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
- /* write serialize memory hole to PCI. Need to unWS when something is
+ /* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index 492ee8fac0..62fa973a8c 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -248,8 +248,8 @@ void cpuRegInit(void)
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
- /* GLIU port active enable, limit south pole masters
- * (AES and PCI) to one outstanding transaction.
+ /* GLIU port active enable, limit south pole masters
+ * (AES and PCI) to one outstanding transaction.
*/
print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index c7b45470e6..53c0a851dc 100644
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
@@ -24,7 +24,7 @@ struct msrinit {
msr_t msr;
};
-static const struct msrinit msr_table[] =
+static const struct msrinit msr_table[] =
{
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
* Rom Properties: Write Serialize, WriteProtect.
@@ -35,7 +35,7 @@ static const struct msrinit msr_table[] =
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
+
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index d5e8338cad..c113f3f8fa 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -5,7 +5,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
-static unsigned long resk(uint64_t value)
+static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
@@ -98,7 +98,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
-
+
}
void amd_setup_mtrrs(void)
@@ -118,7 +118,7 @@ void amd_setup_mtrrs(void)
printk(BIOS_DEBUG, "\n");
/* Initialized the fixed_mtrrs to uncached */
- printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
+ printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
@@ -162,7 +162,7 @@ void amd_setup_mtrrs(void)
wrmsr(i, msr);
}
- /* Enable Variable Mtrrs
+ /* Enable Variable Mtrrs
* Enable the RdMem and WrMem bits in the fixed mtrrs.
* Disable access to the RdMem and WrMem in the fixed mtrr.
*/
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index c56117485a..e6232a8eb4 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -65,13 +65,13 @@ void setupsc520(void)
/* do this to see if MMCR will start acting right. we suspect
* you have to do SOMETHING to get things going. I'm really
- * starting to hate this processor.
+ * starting to hate this processor.
*/
-
- /* no, that did not help. I wonder what will?
+
+ /* no, that did not help. I wonder what will?
* outl(0x800df0cb, 0xfffc);
*/
-
+
/* well, this is special! You have to do SHORT writes to the
* locations, even though they are CHAR in size and CHAR aligned
* and technically, a SHORT write will result in -- yoo ha! --
@@ -80,7 +80,7 @@ void setupsc520(void)
* it now reliably comes up after power cycle with printk. Ah yi
* yi.
*/
-
+
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it. */
sp = (unsigned short *)0xfffef040;
@@ -92,7 +92,7 @@ void setupsc520(void)
/* moved to romstage.c by Stepan, Ron says: */
/* NOTE: move this to mainboard.c ASAP */
setup_pars();
-
+
/* CPCSF register */
sp = (unsigned short *)0xfffefc24;
*sp = 0xfe;
@@ -120,7 +120,7 @@ void setupsc520(void)
/*set the GP RD offset */
sp = (unsigned short *)0xfffefc0c;
*sp = 0x00001;
- /*set the GP WR pulse width*/
+ /*set the GP WR pulse width*/
sp = (unsigned short *)0xfffefc0d;
*sp = 0x00003;
/*set the GP WR offset*/
@@ -164,19 +164,19 @@ void setupsc520(void)
/*; set the interrupt mapping registers.*/
cp = (unsigned char *)0x0fffefd20;
*cp = 0x01;
-
+
cp = (unsigned char *)0x0fffefd28;
*cp = 0x0c;
-
+
cp = (unsigned char *)0x0fffefd29;
*cp = 0x0b;
-
+
cp = (unsigned char *)0x0fffefd30;
*cp = 0x07;
-
+
cp = (unsigned char *)0x0fffefd43;
*cp = 0x03;
-
+
cp = (unsigned char *)0x0fffefd51;
*cp = 0x02;
#endif
@@ -186,8 +186,8 @@ void setupsc520(void)
outl(0x08000683c, 0xcf8);
outl(0xc, 0xcfc); /* set the interrupt line */
-
- /* Set the SC520 PCI host bridge to target mode to
+
+ /* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
@@ -195,7 +195,7 @@ void setupsc520(void)
outl(0x2, 0xcfc); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
-
+
/*
*
@@ -228,7 +228,7 @@ void setupsc520(void)
#define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/
#define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/
-void
+void
dummy_write(void){
volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ;
*ptr = 0;
@@ -247,16 +247,16 @@ static void dumpram(void){
print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
}
-/* there is a lot of silliness in the amd code, and it is
- * causing romcc real headaches, so we're going to be be a little
+/* there is a lot of silliness in the amd code, and it is
+ * causing romcc real headaches, so we're going to be be a little
* less silly.
- * so, the order of ops is:
+ * so, the order of ops is:
* for i in 3 to 0
- * see if bank is there.
+ * see if bank is there.
* if we can write a word, and read it back, to hell with paranoia
- * the bank is there. So write the magic byte, read it back, and
- * use that to get size, etc. Try to keep things very simple,
- * so people can actually follow the damned code.
+ * the bank is there. So write the magic byte, read it back, and
+ * use that to get size, etc. Try to keep things very simple,
+ * so people can actually follow the damned code.
*/
/* cache is assumed to be disabled */
@@ -273,14 +273,14 @@ int sizemem(void)
/* no ecc interrupts of any kind. */
*eccctl = 0;
/* Set SDRAM timing for slowest speed. */
- *drcmctl = 0x1e;
+ *drcmctl = 0x1e;
/* setup dram register for all banks
* with max cols and max banks
* this is the oldest trick in the book. You are going to set up for max rows
- * and cols, then do a write, then see if the data is wrapped to low memory.
- * you can actually tell by which data gets to which low memory,
- * exactly how many rows and cols you have.
+ * and cols, then do a write, then see if the data is wrapped to low memory.
+ * you can actually tell by which data gets to which low memory,
+ * exactly how many rows and cols you have.
*/
*drccfg=0xbbbb;
@@ -339,24 +339,24 @@ int sizemem(void)
*lp = 0xdeadbeef;
print_err("assigned l ... \n");
if (*lp != 0xdeadbeef) {
- print_err(" no memory at bank ");
- // print_err_hex8(bank);
+ print_err(" no memory at bank ");
+ // print_err_hex8(bank);
// print_err(" value "); print_err_hex32(*lp);
- print_err("\n");
+ print_err("\n");
// continue;
}
*drcctl = 2;
dummy_write();
*drccfg = *drccfg >> 4;
l = *drcbendadr;
- l >>= 8;
+ l >>= 8;
*drcbendadr = l;
print_err("loop around\n");
*drcctl = 0;
dummy_write();
}
#if 0
- /* enable last bank and setup ending address
+ /* enable last bank and setup ending address
* register for max ram in last bank
*/
*drcbendadr=0x0ff000000;
@@ -410,10 +410,10 @@ int sizemem(void)
bank = 3;
- /* this is really ugly, it is right from assembly code.
+ /* this is really ugly, it is right from assembly code.
* we need to clean it up later
*/
-
+
start:
/* write col 11 wrap adr */
COL11_ADR=COL11_DATA;
@@ -519,7 +519,7 @@ print_err("4b\n");
print_err("cols"); print_err_hex32(cols); print_err("\n");
cols -= COL08_DATA;
- /* cols now is in the range of 0 1 2 3 ...
+ /* cols now is in the range of 0 1 2 3 ...
*/
i = cols&3;
// i = cols + rows;
@@ -533,22 +533,22 @@ print_err("4b\n");
/* what a fookin' mess this is */
if(banks==4)
i+=8; /* <-- i holds merged value */
- /* i now has the col width in bits 0-1 and the bank count (2 or 4)
+ /* i now has the col width in bits 0-1 and the bank count (2 or 4)
* in bit 3.
- * this is the format for the drccfg register
+ * this is the format for the drccfg register
*/
-
+
/* fix ending addr mask*/
/*FIXME*/
/* let's just go with this to start ... see if we can get ANYWHERE */
/* need to get end addr. Need to do it with the bank in mind. */
/*
- al = 3;
+ al = 3;
al -= i&3;
*drcbendaddr = rows >> al;
- print_err("computed ending_adr = "); print_err_hex8(ending_adr);
+ print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("\n");
-
+
*/
bad_reinit:
/* issue all banks recharge */
@@ -557,7 +557,7 @@ bad_reinit:
/* update ending address register */
// *drcbendadr = ending_adr;
-
+
/* update config register */
*drccfg &= ~(0xff << bank*4);
if (ending_adr)
@@ -579,11 +579,11 @@ bad_reinit:
*drcctl=0x18;
dummy_write();
return bank;
-
+
bad_ram:
print_info("bad ram!\n");
- /* you are here because the read-after-write failed,
- * in most cases because: no ram in that bank!
+ /* you are here because the read-after-write failed,
+ * in most cases because: no ram in that bank!
* set badbank to 1 and go to reinit
*/
ending_adr = 0;
@@ -591,7 +591,7 @@ bad_ram:
while(1)
print_err("DONE NEXTBANK\n");
#endif
-}
+}
/* note: based on AMD code*/
/* This code is known to work on the digital logic board and on the technologic
@@ -600,7 +600,7 @@ bad_ram:
int staticmem(void)
{
volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
-
+
/* set up 0x18 .. **/
*drcbendadr = 0x88;
*drcmctl = 0x1e;
@@ -609,7 +609,7 @@ int staticmem(void)
*drcctl = 0x1;
/* do the dummy write */
*zero = 0;
-
+
/* precharge */
*drcctl = 2;
*zero = 0;
@@ -625,7 +625,7 @@ int staticmem(void)
*drcctl = 3;
*zero = 0;
print_debug("DONE the load mode reg\n");
-
+
/* normal mode */
*drcctl = 0x0;
*zero = 0;
@@ -634,7 +634,7 @@ int staticmem(void)
*zero = 0;
print_debug("DONE the normal\n");
*zero = 0xdeadbeef;
- if (*zero != 0xdeadbeef)
+ if (*zero != 0xdeadbeef)
print_debug("NO LUCK\n");
else
print_debug("did a store and load ...\n");
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index e867fae3d7..4c93ebd295 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -16,10 +16,10 @@
#include "chip.h"
/*
- * set up basic things ...
- * PAR should NOT go here, as it might change with the mainboard.
+ * set up basic things ...
+ * PAR should NOT go here, as it might change with the mainboard.
*/
-static void cpu_init(device_t dev)
+static void cpu_init(device_t dev)
{
unsigned long *l = (unsigned long *) 0xfffef088;
int i;
@@ -30,9 +30,9 @@ static void cpu_init(device_t dev)
}
-/* Ollie says: make a northbridge/amd/sc520. Ron sez:
- * there is no real northbridge, keep it here in cpu.
- * Ron wins, he's writing the code.
+/* Ollie says: make a northbridge/amd/sc520. Ron sez:
+ * there is no real northbridge, keep it here in cpu.
+ * Ron wins, he's writing the code.
*/
static void sc520_enable_resources(struct device *dev) {
unsigned char command;
@@ -141,16 +141,16 @@ static void pci_domain_set_resources(device_t dev)
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
- /* these are ENDING addresses, not sizes.
+ /* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
- * So we just take the max, that gives us total.
+ * So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
- printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
+ printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@@ -245,5 +245,5 @@ static void enable_dev(struct device *dev)
struct chip_operations cpu_amd_sc520_ops = {
CHIP_NAME("AMD Elan SC520 CPU")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};