diff options
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/car/clear_init_ram.c | 45 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 34 |
2 files changed, 25 insertions, 54 deletions
diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index 593c0ddfd6..ff05f0d439 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -11,49 +11,8 @@ static void __attribute__((noinline)) clear_init_ram(void) } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ -static inline __attribute__((always_inline)) void set_init_ram_access(void) +static void set_init_ram_access(void) { - __asm__ volatile ( - - "pushl %%ecx\n\t" - "pushl %%edx\n\t" - "pushl %%eax\n\t" - - /* enable caching for first 1M using variable mtrr */ - "movl $0x200, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $(0 | 6), %%eax\n\t" -// "movl $(0 | MTRR_TYPE_WRBACK), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x201, %%ecx\n\t" - "movl $0x0000000f, %%edx\n\t" -#if CONFIG_USE_INIT - "movl %%esi, %%eax\n\t" -#else - "movl $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t" -#endif - "wrmsr\n\t" - -#if 0 - /* enable caching for 64K using fixed mtrr */ - "movl $0x26e, %%ecx\n\t" /* fix4k_f0000*/ - "movl $0x1e1e1e1e, %%eax\n\t" /* WB MEM type */ - "movl %%eax, %%edx\n\t" - "wrmsr\n\t" - "movl $0x26f, %%ecx\n\t" /* fix4k_f8000*/ - "wrmsr\n\t" -#endif - - "popl %%eax\n\t" - "popl %%edx\n\t" - "popl %%ecx\n\t" - - : - : -#if CONFIG_USE_INIT - "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800) -#endif - ); + set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRBACK); } diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index e60aa35bf9..50b1532f26 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -10,7 +10,10 @@ typedef void (*process_ap_t)(unsigned apicid, void *gp); -static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t process_ap, void *gp) +//core_range = 0 : all cores +//core range = 1 : core 0 only +//core range = 2 : cores other than core0 +static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t process_ap, void *gp) { // here assume the OS don't change our apicid unsigned ap_apicid; @@ -49,16 +52,20 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t p } siblings = j; - unsigned jj; + unsigned jstart, jend; + + if(core_range == 2) { + jstart = 1; + } + + if(e0_later_single_core || disable_siblings || (core_range==1)) { + jend = 0; + } else { + jend = siblings; + } - if(e0_later_single_core || disable_siblings || core0_only) { - jj = 0; - } else { - jj = siblings; - } - - - for(j=0; j<=jj; j++) { + + for(j=jstart; j<=jend; j++) { ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); @@ -145,6 +152,11 @@ static void wait_all_aps_started(unsigned bsp_apicid) for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); } +static void wait_all_other_cores_started(unsigned bsp_apicid) +{ + for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); +} + static void allow_all_aps_stop(unsigned bsp_apicid) { lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop @@ -243,7 +255,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) wait_cpu_state(bsp_apicid, 0x44); lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu - set_init_ram_access(); //inline + set_init_ram_access(); disable_cache_as_ram(); // inline stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } |