diff options
Diffstat (limited to 'src/cpu/i386')
| -rw-r--r-- | src/cpu/i386/bist32.inc | 4 | ||||
| -rw-r--r-- | src/cpu/i386/bist32_fail.inc | 44 | ||||
| -rw-r--r-- | src/cpu/i386/entry16.inc | 5 | ||||
| -rw-r--r-- | src/cpu/i386/entry32.inc | 6 |
4 files changed, 59 insertions, 0 deletions
diff --git a/src/cpu/i386/bist32.inc b/src/cpu/i386/bist32.inc new file mode 100644 index 0000000000..d2fb98cdc3 --- /dev/null +++ b/src/cpu/i386/bist32.inc @@ -0,0 +1,4 @@ + + /* Carefully print the failure if the built in self test did not pass */ + testl %eax, %eax + jnz bist32_fail diff --git a/src/cpu/i386/bist32_fail.inc b/src/cpu/i386/bist32_fail.inc new file mode 100644 index 0000000000..f467b065bc --- /dev/null +++ b/src/cpu/i386/bist32_fail.inc @@ -0,0 +1,44 @@ + + + jmp bist32_fail_0 +bist32_fail: + movl %eax, %ebp + +#if 1 +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA SIO_BASE+1 +#define SIO_WRITE_CONFIG(value, reg) \ + movb reg, %al ; \ + outb %al, $(SIO_INDEX) ; \ + movb value, %al ; \ + outb %al, $(SIO_DATA) + +#define SIO_READ_CONFIG(reg) \ + movb reg, %al ; \ + outb %al, $(SIO_INDEX) ; \ + inb $(SIO_DATA), %al + +#define SIO_SET_LOGICAL_DEVICE(device) \ + SIO_WRITE_CONFIG(device, $0x07) + + /* Enable serial 1 */ + SIO_SET_LOGICAL_DEVICE($3) + SIO_WRITE_CONFIG($1, $0x30) + SIO_WRITE_CONFIG($0x3, $0x60) + SIO_WRITE_CONFIG($0xf8, $0x61) + +#endif + CALLSP(serial_init) + CONSOLE_DEBUG_TX_STRING($str_bist_failed) + CONSOLE_DEBUG_TX_HEX32(%ebp) + CONSOLE_DEBUG_TX_STRING($str_bist_newline) + jmp .Lhlt + +bist32_fail_0: + +.section ".rom.data" +str_bist_failed: .string "BIST failed: " +str_bist_newline: .string "\r\n" +.previous + diff --git a/src/cpu/i386/entry16.inc b/src/cpu/i386/entry16.inc index 7ab3ff3bf0..f9e921f291 100644 --- a/src/cpu/i386/entry16.inc +++ b/src/cpu/i386/entry16.inc @@ -33,6 +33,8 @@ it with the version available from LANL. _start: cli + /* Save the BIST result */ + movl %eax, %ebp /* thanks to kmliu@sis.tw.com for this TBL fix ... */ /**/ @@ -93,6 +95,9 @@ _start: orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 + /* Restore BIST to %eax */ + movl %ebp, %eax + /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp $ROM_CODE_SEG, $__protected_start diff --git a/src/cpu/i386/entry32.inc b/src/cpu/i386/entry32.inc index 6f55f00203..3d30a3f85f 100644 --- a/src/cpu/i386/entry32.inc +++ b/src/cpu/i386/entry32.inc @@ -44,6 +44,9 @@ protected_start: ljmp $ROM_CODE_SEG, $__protected_start __protected_start: + /* Save the BIST value */ + movl %eax, %ebp + intel_chip_post_macro(0x10) /* post 10 */ movw $ROM_DATA_SEG, %ax @@ -53,3 +56,6 @@ __protected_start: movw %ax, %fs movw %ax, %gs + /* Restore the BIST value to %eax */ + movl %ebp, %eax + |