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Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig new file mode 100644 index 0000000000..406f8a5c95 --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -0,0 +1,93 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + +config CPU_INTEL_FSP_MODEL_206AX + bool + +config CPU_INTEL_FSP_MODEL_306AX + bool + +if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMP + select SSE2 + select UDELAY_LAPIC + select SMM_TSEG + select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN + select BOARD_MICROCODE_CBFS_GENERATE + select TSC_SYNC_MFENCE + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/fsp_model_206ax/bootblock.c" + +config SERIAL_CPU_INIT + bool + default n + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +config CPU_MICROCODE_CBFS_LOC + hex + depends on CPU_MICROCODE_IN_CBFS + default 0xfff70000 + +config CPU_MICROCODE_CBFS_LEN + hex + depends on CPU_MICROCODE_IN_CBFS + default 0xC000 if CPU_INTEL_FSP_MODEL_306AX + default 0x2800 if CPU_INTEL_FSP_MODEL_206AX + +config MICROCODE_INCLUDE_PATH + string "Location of the intel microcode patches" + default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX + default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX + +config FSP_IMAGE_ID_DWORD0 + hex + default 0x2D325453 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX + default 0x2D324343 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X + help + The FSP Image ID is different for each platform's FSP and can be used to + verify that the right FSP binary is loaded. + For the ivybridge/89xx FSP, the Image Id will be "ST2-FSP\0", + for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0", + This dword holds the first 4 bytes of the string, as + a hex value. + +config FSP_IMAGE_ID_DWORD1 + hex + default 0x00505346 + help + For the ivybridge/I89xx FSP, the Image Id will be "ST2-FSP\0", + for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0", + This dword holds the second 4 bytes of the string, as + a hex value. Since the strings use the same second dword, + no additional logic is needed. + +endif |