diff options
Diffstat (limited to 'src/cpu/intel/haswell/romstage.c')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index edb2e80cdd..40a396d501 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -108,18 +108,18 @@ static void *setup_romstage_stack_after_car(void) * of physical address bits. */ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - /* The order for each MTTR is value then base with upper 32-bits of + /* The order for each MTRR is value then base with upper 32-bits of * each value coming before the lower 32-bits. The reasoning for * this ordering is to create a stack layout like the following: * +0: Number of MTRRs - * +4: MTTR base 0 31:0 - * +8: MTTR base 0 63:32 - * +12: MTTR mask 0 31:0 - * +16: MTTR mask 0 63:32 - * +20: MTTR base 1 31:0 - * +24: MTTR base 1 63:32 - * +28: MTTR mask 1 31:0 - * +32: MTTR mask 1 63:32 + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 */ /* Cache the ROM as WP just below 4GiB. */ @@ -158,7 +158,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; - /* Save the number of MTTRs to setup. Return the stack location + /* Save the number of MTRRs to setup. Return the stack location * pointing to the number of MTRRs. */ slot = stack_push(slot, num_mtrrs); |