diff options
Diffstat (limited to 'src/cpu/intel/haswell/stage_cache.c')
| -rw-r--r-- | src/cpu/intel/haswell/stage_cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index ee945c772f..009cc09ba6 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -20,7 +20,7 @@ void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of ram is defined to be the TSEG base address. */ + * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } |