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-rw-r--r--src/cpu/intel/microcode/Kconfig2
-rw-r--r--src/cpu/intel/microcode/microcode.c18
2 files changed, 2 insertions, 18 deletions
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
index 73afe0bb45..238aad745d 100644
--- a/src/cpu/intel/microcode/Kconfig
+++ b/src/cpu/intel/microcode/Kconfig
@@ -1,7 +1,7 @@
config MICROCODE_UPDATE_PRE_RAM
bool
depends on SUPPORT_CPU_UCODE_IN_CBFS
- default y if !ROMCC_BOOTBLOCK
+ default y
help
Select this option if you want to update the microcode
during the cache as ram setup.
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 80470bf236..90138be236 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -15,11 +15,7 @@
#include <stdint.h>
#include <stddef.h>
-#if !defined(__ROMCC__)
#include <cbfs.h>
-#else
-#include <arch/cbfs.h>
-#endif
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
@@ -141,22 +137,11 @@ const void *intel_microcode_find(void)
unsigned int x86_model, x86_family;
msr_t msr;
-#ifdef __ROMCC__
- struct cbfs_file *microcode_file;
-
- microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE);
- if (!microcode_file)
- return NULL;
-
- ucode_updates = CBFS_SUBHEADER(microcode_file);
- microcode_len = ntohl(microcode_file->len);
-#else
ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE,
CBFS_TYPE_MICROCODE,
&microcode_len);
if (ucode_updates == NULL)
return NULL;
-#endif
/* CPUID sets MSR 0x8B if a microcode update has been loaded. */
msr.lo = 0;
@@ -201,8 +186,7 @@ const void *intel_microcode_find(void)
microcode_len -= update_size;
}
- /* ROMCC doesn't like NULL. */
- return (void *)0;
+ return NULL;
}
void intel_update_microcode_from_cbfs(void)