diff options
Diffstat (limited to 'src/cpu/intel/model_206ax/bootblock.c')
| -rw-r--r-- | src/cpu/intel/model_206ax/bootblock.c | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 72b4a672c2..da0333f4bc 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -13,13 +13,11 @@ #include <stdint.h> #include <arch/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> +#include <cpu/intel/car/bootblock.h> -#include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ @@ -30,35 +28,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -109,10 +78,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } |