diff options
Diffstat (limited to 'src/cpu/intel/model_206ax')
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index c4d3701c48..7d402e4d4e 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cbmem.h> @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -126,7 +127,7 @@ clear_mtrrs: post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ @@ -162,7 +163,7 @@ clear_mtrrs: post_code(0x28) /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer below MRC variable space. */ @@ -195,7 +196,7 @@ before_romstage: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -235,14 +236,14 @@ before_romstage: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -275,7 +276,7 @@ before_romstage: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) |