summaryrefslogtreecommitdiff
path: root/src/cpu/intel/model_6ex
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index f4c4af86d3..79383e163f 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -135,8 +135,8 @@ clear_mtrrs:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
+ * after cache-as-ram is torn down.
+ */
movl %eax, %ebx
post_code(0x2f)