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-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc12
1 files changed, 2 insertions, 10 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 2b74918859..d4f5d8bf5e 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -21,6 +21,7 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
@@ -256,16 +257,7 @@ __main:
movl %ebp, %esi
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
- * makes sure that we stay completely within the 1M-64K of memory that we
- * preserve for suspend/resume.
- */
-
-#ifndef HIGH_MEMORY_SAVE
-#warning Need a central place for HIGH_MEMORY_SAVE
-#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
-#endif
- movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
+ movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
pushl %esi
call copy_and_run