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-rw-r--r--src/cpu/intel/slot_1/Kconfig1
-rw-r--r--src/cpu/intel/slot_1/Makefile.inc1
-rw-r--r--src/cpu/intel/slot_1/l2_cache.c1
-rw-r--r--src/cpu/intel/slot_1/slot_1.c1
4 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 35b1913377..1ba71ad9cb 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -1,5 +1,4 @@
##
-## This file is part of the coreboot project.
##
## SPDX-License-Identifier: GPL-2.0-only
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index 66651fc5a3..03026cc0c4 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -1,4 +1,3 @@
-## This file is part of the coreboot project.
## SPDX-License-Identifier: GPL-2.0-or-later
ramstage-y += slot_1.c
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
index 518d5813a0..ce3634b667 100644
--- a/src/cpu/intel/slot_1/l2_cache.c
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -1,4 +1,3 @@
-/* This file is part of the coreboot project. */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c
index e540548206..0f5b157eca 100644
--- a/src/cpu/intel/slot_1/slot_1.c
+++ b/src/cpu/intel/slot_1/slot_1.c
@@ -1,4 +1,3 @@
-/* This file is part of the coreboot project. */
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/device.h>