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-rw-r--r--src/cpu/intel/socket_m/Kconfig23
-rw-r--r--src/cpu/intel/socket_m/Makefile.inc17
2 files changed, 40 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
new file mode 100644
index 0000000000..aadc9a47b0
--- /dev/null
+++ b/src/cpu/intel/socket_m/Kconfig
@@ -0,0 +1,23 @@
+config CPU_INTEL_SOCKET_M
+ bool
+
+if CPU_INTEL_SOCKET_M
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_MODEL_69X
+ select CPU_INTEL_MODEL_6DX
+ select CPU_INTEL_MODEL_6EX
+ select CPU_INTEL_MODEL_6FX
+ select MMX
+ select SSE
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xfefc0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif
diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
new file mode 100644
index 0000000000..139b1bb624
--- /dev/null
+++ b/src/cpu/intel/socket_m/Makefile.inc
@@ -0,0 +1,17 @@
+subdirs-y += ../model_69x
+subdirs-y += ../model_6dx
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
+
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+
+romstage-y += ../car/romstage.c