summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_f2x/Config.lb9
-rw-r--r--src/cpu/intel/model_f2x/apic_timer.c26
2 files changed, 34 insertions, 1 deletions
diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb
index 508e1da172..b985ffc12d 100644
--- a/src/cpu/intel/model_f2x/Config.lb
+++ b/src/cpu/intel/model_f2x/Config.lb
@@ -1,4 +1,5 @@
-dir /cpu/x86/tsc
+uses CONFIG_UDELAY_TSC
+
dir /cpu/x86/mtrr
dir /cpu/x86/fpu
dir /cpu/x86/mmx
@@ -8,3 +9,9 @@ dir /cpu/x86/cache
dir /cpu/intel/microcode
dir /cpu/intel/hyperthreading
driver model_f2x_init.o
+
+if CONFIG_UDELAY_TSC
+ dir /cpu/x86/tsc
+else
+ object apic_timer.o
+end
diff --git a/src/cpu/intel/model_f2x/apic_timer.c b/src/cpu/intel/model_f2x/apic_timer.c
new file mode 100644
index 0000000000..5a81f912c5
--- /dev/null
+++ b/src/cpu/intel/model_f2x/apic_timer.c
@@ -0,0 +1,26 @@
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+
+void init_timer(void)
+{
+ /* Set the apic timer to no interrupts and periodic mode */
+ lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
+ /* Set the divider to 1, no divider */
+ lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
+ /* Set the initial counter to 0xffffffff */
+ lapic_write(LAPIC_TMICT, 0xffffffff);
+}
+
+void udelay(unsigned usecs)
+{
+ uint32_t start, value, ticks;
+ /* Calculate the number of ticks to run, our FSB runs a 200Mhz */
+ ticks = usecs * 200;
+ start = lapic_read(LAPIC_TMCCT);
+ do {
+ value = lapic_read(LAPIC_TMCCT);
+ } while((start - value) < ticks);
+
+}