diff options
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 12 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 12 |
3 files changed, 14 insertions, 14 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 3949a567c8..fc4eb8ae74 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -354,7 +354,7 @@ lout: */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr /* Enable cache. */ diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index fc4947600f..0ee26fcdd2 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -63,14 +63,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -118,7 +118,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -160,7 +160,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -201,7 +201,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -217,7 +217,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index a1b82675fb..a7605cc689 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -70,14 +70,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -125,7 +125,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -167,7 +167,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -208,7 +208,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -224,7 +224,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) |