4 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/samsung/exynos5-common/pwm.c b/src/cpu/samsung/exynos5-common/pwm.c
index da465d93c7..0fc571b220 100644
--- a/src/cpu/samsung/exynos5-common/pwm.c
+++ b/src/cpu/samsung/exynos5-common/pwm.c
@@ -32,7 +32,7 @@
 int pwm_enable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
-			(struct s5p_timer *)samsung_get_base_timer();
+			samsung_get_base_timer();
 	unsigned long tcon;
 
 	tcon = readl(&pwm->tcon);
@@ -46,7 +46,7 @@ int pwm_enable(int pwm_id)
 int pwm_check_enabled(int pwm_id)
 {
 	const struct s5p_timer *pwm =
-			(struct s5p_timer *)samsung_get_base_timer();
+			samsung_get_base_timer();
 	const unsigned long tcon = readl(&pwm->tcon);
 
 	return tcon & TCON_START(pwm_id);
@@ -55,7 +55,7 @@ int pwm_check_enabled(int pwm_id)
 void pwm_disable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
-			(struct s5p_timer *)samsung_get_base_timer();
+			samsung_get_base_timer();
 	unsigned long tcon;
 
 	tcon = readl(&pwm->tcon);
@@ -84,7 +84,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
 int pwm_config(int pwm_id, int duty_ns, int period_ns)
 {
 	const struct s5p_timer *pwm =
-			(struct s5p_timer *)samsung_get_base_timer();
+			samsung_get_base_timer();
 	unsigned int offset;
 	unsigned long tin_rate;
 	unsigned long tin_ns;
@@ -143,7 +143,7 @@ int pwm_init(int pwm_id, int div, int invert)
 {
 	u32 val;
 	const struct s5p_timer *pwm =
-			(struct s5p_timer *)samsung_get_base_timer();
+			samsung_get_base_timer();
 	unsigned long ticks_per_period;
 	unsigned int offset, prescaler;
 
diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5-common/sromc.c
index 091e8d18ab..7bc93e7862 100644
--- a/src/cpu/samsung/exynos5-common/sromc.c
+++ b/src/cpu/samsung/exynos5-common/sromc.c
@@ -36,7 +36,7 @@ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
 {
 	u32 tmp;
 	struct s5p_sromc *srom =
-		(struct s5p_sromc *)samsung_get_base_sromc();
+		samsung_get_base_sromc();
 
 	/* Configure SMC_BW register to handle proper SROMC bank */
 	tmp = srom->bw;
diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c
index 6436da2770..6cd5f5dd35 100644
--- a/src/cpu/samsung/exynos5-common/timer.c
+++ b/src/cpu/samsung/exynos5-common/timer.c
@@ -39,7 +39,7 @@ static unsigned long lastinc;
 /* macro to read the 16 bit timer */
 static inline struct s5p_timer *s5p_get_base_timer(void)
 {
-	return (struct s5p_timer *)samsung_get_base_timer();
+	return samsung_get_base_timer();
 }
 
 /**
diff --git a/src/cpu/samsung/exynos5-common/wdt.c b/src/cpu/samsung/exynos5-common/wdt.c
index 6f435e5857..dbeefec49a 100644
--- a/src/cpu/samsung/exynos5-common/wdt.c
+++ b/src/cpu/samsung/exynos5-common/wdt.c
@@ -30,7 +30,7 @@
 void wdt_stop(void)
 {
 	struct s5p_watchdog *wdt =
-		(struct s5p_watchdog *)samsung_get_base_watchdog();
+		samsung_get_base_watchdog();
 	unsigned int wtcon;
 
 	wtcon = readl(&wdt->wtcon);
@@ -42,7 +42,7 @@ void wdt_stop(void)
 void wdt_start(unsigned int timeout)
 {
 	struct s5p_watchdog *wdt =
-		(struct s5p_watchdog *)samsung_get_base_watchdog();
+		samsung_get_base_watchdog();
 	unsigned int wtcon;
 
 	wdt_stop();