1 files changed, 6 insertions, 97 deletions

diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h
index 00561a0b58..3757e7d761 100644
--- a/src/cpu/samsung/exynos5250/clock_init.h
+++ b/src/cpu/samsung/exynos5250/clock_init.h
@@ -25,10 +25,6 @@
 #ifndef __EXYNOS_CLOCK_INIT_H
 #define __EXYNOS_CLOCK_INIT_H
 
-enum {
-	MEM_TIMINGS_MSR_COUNT	= 4,
-};
-
 /* These are the ratio's for configuring ARM clock */
 struct arm_clk_ratios {
 	unsigned int arm_freq_mhz;	/* Frequency of ARM core in MHz */
@@ -47,104 +43,17 @@ struct arm_clk_ratios {
 	unsigned int arm_ratio;
 };
 
-/* These are the memory timings for a particular memory type and speed */
-struct mem_timings {
-	enum mem_manuf mem_manuf;	/* Memory manufacturer */
-	enum ddr_mode mem_type;		/* Memory type */
-	unsigned int frequency_mhz;	/* Frequency of memory in MHz */
-
-	/* Here follow the timing parameters for the selected memory */
-	uint8_t apll_mdiv;
-	uint8_t apll_pdiv;
-	uint8_t apll_sdiv;
-	uint8_t mpll_mdiv;
-	uint8_t mpll_pdiv;
-	uint8_t mpll_sdiv;
-	uint8_t cpll_mdiv;
-	uint8_t cpll_pdiv;
-	uint8_t cpll_sdiv;
-	uint8_t gpll_pdiv;
-	uint16_t gpll_mdiv;
-	uint8_t gpll_sdiv;
-	uint8_t epll_mdiv;
-	uint8_t epll_pdiv;
-	uint8_t epll_sdiv;
-	uint8_t vpll_mdiv;
-	uint8_t vpll_pdiv;
-	uint8_t vpll_sdiv;
-	uint8_t bpll_mdiv;
-	uint8_t bpll_pdiv;
-	uint8_t bpll_sdiv;
-	uint8_t use_bpll;       /* 1 to use BPLL for cdrex, 0 to use MPLL */
-	uint8_t pclk_cdrex_ratio;
-	unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
-
-	unsigned int timing_ref;
-	unsigned int timing_row;
-	unsigned int timing_data;
-	unsigned int timing_power;
-
-	/* DQS, DQ, DEBUG offsets */
-	unsigned int phy0_dqs;
-	unsigned int phy1_dqs;
-	unsigned int phy0_dq;
-	unsigned int phy1_dq;
-	uint8_t phy0_tFS;
-	uint8_t phy1_tFS;
-	uint8_t phy0_pulld_dqs;
-	uint8_t phy1_pulld_dqs;
-
-	uint8_t lpddr3_ctrl_phy_reset;
-	uint8_t ctrl_start_point;
-	uint8_t ctrl_inc;
-	uint8_t ctrl_start;
-	uint8_t ctrl_dll_on;
-	uint8_t ctrl_ref;
-
-	uint8_t ctrl_force;
-	uint8_t ctrl_rdlat;
-	uint8_t ctrl_bstlen;
-
-	uint8_t fp_resync;
-	uint8_t iv_size;
-	uint8_t dfi_init_start;
-	uint8_t aref_en;
-
-	uint8_t rd_fetch;
-
-	uint8_t zq_mode_dds;
-	uint8_t zq_mode_term;
-	uint8_t zq_mode_noterm;	/* 1 to allow termination disable */
-
-	unsigned int memcontrol;
-	unsigned int memconfig;
-
-	unsigned int membaseconfig0;
-	unsigned int membaseconfig1;
-	unsigned int prechconfig_tp_cnt;
-	unsigned int dpwrdn_cyc;
-	unsigned int dsref_cyc;
-	unsigned int concontrol;
-	/* Channel and Chip Selection */
-	uint8_t dmc_channels;		/* number of memory channels */
-	uint8_t chips_per_channel;	/* number of chips per channel */
-	uint8_t chips_to_configure;	/* number of chips to configure */
-	uint8_t send_zq_init;		/* 1 to send this command */
-	unsigned int impedance;		/* drive strength impedeance */
-	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
-};
-
 /**
- * Get the correct memory timings for our selected memory type and speed.
- *
- * This function can be called from SPL or the main U-Boot.
+ * Get the clock ratios for CPU configuration
  *
- * @return pointer to the memory timings that we should use
+ * @return pointer to the clock ratios that we should use
  */
-struct mem_timings *clock_get_mem_timings(void);
+struct arm_clk_ratios *get_arm_clk_ratios(void);
 
 /*
  * Initialize clock for the device
  */
-void system_clock_init(void);
+struct mem_timings;
+void system_clock_init(struct mem_timings *mem,
+		struct arm_clk_ratios *arm_clk_ratio);
 #endif