diff options
Diffstat (limited to 'src/cpu/samsung/exynos5250/dmc_init_ddr3.c')
| -rw-r--r-- | src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 137 |
1 files changed, 65 insertions, 72 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index f2c228d339..89a7b613e7 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -19,9 +19,9 @@ /* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */ -#include <console/console.h> #include <delay.h> #include <arch/io.h> +#include <console/console.h> #include "clk.h" #include "cpu.h" #include "dmc.h" @@ -31,10 +31,8 @@ static void reset_phy_ctrl(void) { - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - - writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &exynos_clock->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &exynos_clock->lpddr3phy_ctrl); #if 0 /* @@ -57,14 +55,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, int mem_reset) { unsigned int val; - struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; - struct exynos5_dmc *dmc; int i; - phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; - phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; - dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - if (mem_reset) reset_phy_ctrl(); @@ -73,90 +65,90 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); - writel(val, &phy0_ctrl->phy_con39); - writel(val, &phy1_ctrl->phy_con39); + writel(val, &exynos_phy0_control->phy_con39); + writel(val, &exynos_phy1_control->phy_con39); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &phy0_ctrl->phy_con42); - writel(val, &phy1_ctrl->phy_con42); + writel(val, &exynos_phy0_control->phy_con42); + writel(val, &exynos_phy1_control->phy_con42); /* ZQ Calibration */ - if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) { + if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){ printk(BIOS_EMERG, "DRAM ZQ CALIBRATION FAILURE\n"); return SETUP_ERR_ZQ_CALIBRATION_FAILURE; } /* DQ Signal */ - writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); - writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); + writel(mem->phy0_pulld_dqs, &exynos_phy0_control->phy_con14); + writel(mem->phy1_pulld_dqs, &exynos_phy1_control->phy_con14); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), - &dmc->concontrol); + &exynos_dmc->concontrol); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(exynos_dmc, DDR_MODE_DDR3); /* DQS Signal */ - writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); - writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); + writel(mem->phy0_dqs, &exynos_phy0_control->phy_con4); + writel(mem->phy1_dqs, &exynos_phy1_control->phy_con4); - writel(mem->phy0_dq, &phy0_ctrl->phy_con6); - writel(mem->phy1_dq, &phy1_ctrl->phy_con6); + writel(mem->phy0_dq, &exynos_phy0_control->phy_con6); + writel(mem->phy1_dq, &exynos_phy1_control->phy_con6); - writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); - writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); + writel(mem->phy0_tFS, &exynos_phy0_control->phy_con10); + writel(mem->phy1_tFS, &exynos_phy1_control->phy_con10); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); + writel(val, &exynos_phy0_control->phy_con12); + writel(val, &exynos_phy1_control->phy_con12); /* Start DLL locking */ writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy0_ctrl->phy_con12); + &exynos_phy0_control->phy_con12); writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy1_ctrl->phy_con12); + &exynos_phy1_control->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(exynos_dmc, DDR_MODE_DDR3); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &dmc->concontrol); + &exynos_dmc->concontrol); - /* Memory Channel Interleaving Size */ - writel(mem->iv_size, &dmc->ivcontrol); + /* Memory Channel Inteleaving Size */ + writel(mem->iv_size, &exynos_dmc->ivcontrol); /* Set DMC MEMCONTROL register */ val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; - writel(val, &dmc->memcontrol); + writel(val, &exynos_dmc->memcontrol); - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(mem->membaseconfig0, &dmc->membaseconfig0); - writel(mem->membaseconfig1, &dmc->membaseconfig1); + writel(mem->memconfig, &exynos_dmc->memconfig0); + writel(mem->memconfig, &exynos_dmc->memconfig1); + writel(mem->membaseconfig0, &exynos_dmc->membaseconfig0); + writel(mem->membaseconfig1, &exynos_dmc->membaseconfig1); /* Precharge Configuration */ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &dmc->prechconfig); + &exynos_dmc->prechconfig); /* Power Down mode Configuration */ writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, - &dmc->pwrdnconfig); + &exynos_dmc->pwrdnconfig); /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters */ - writel(mem->timing_ref, &dmc->timingref); - writel(mem->timing_row, &dmc->timingrow); - writel(mem->timing_data, &dmc->timingdata); - writel(mem->timing_power, &dmc->timingpower); + writel(mem->timing_ref, &exynos_dmc->timingref); + writel(mem->timing_row, &exynos_dmc->timingrow); + writel(mem->timing_data, &exynos_dmc->timingdata); + writel(mem->timing_power, &exynos_dmc->timingpower); /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, exynos_dmc); if (mem_reset) { /* Send NOP, MRS and ZQINIT commands. @@ -164,25 +156,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, * reseting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset */ - dmc_config_mrs(mem, dmc); + dmc_config_mrs(mem, exynos_dmc); } if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); + writel(val, &exynos_phy0_control->phy_con0); + writel(val, &exynos_phy1_control->phy_con0); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); + writel(val, &exynos_phy0_control->phy_con2); + writel(val, &exynos_phy1_control->phy_con2); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); + writel(val, &exynos_phy0_control->phy_con0); + writel(val, &exynos_phy1_control->phy_con0); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -190,30 +182,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); + writel(val, &exynos_phy0_control->phy_con12); + writel(val, &exynos_phy1_control->phy_con12); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; val |= RDLVL_GATE_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); + writel(val, &exynos_phy0_control->phy_con2); + writel(val, &exynos_phy1_control->phy_con2); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; val |= CTRL_SHGATE; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); + writel(val, &exynos_phy0_control->phy_con0); + writel(val, &exynos_phy1_control->phy_con0); val = PHY_CON1_RESET_VAL; val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &phy0_ctrl->phy_con1); - writel(val, &phy1_ctrl->phy_con1); + writel(val, &exynos_phy0_control->phy_con1); + writel(val, &exynos_phy1_control->phy_con1); - writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); + writel(CTRL_RDLVL_GATE_ENABLE, &exynos_dmc->rdlvl_config); i = RDLVL_COMPLETE_TIMEOUT; - while ((readl(&dmc->phystatus) & + while ((readl(&exynos_dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { /* @@ -227,10 +219,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n"); return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; } - writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config); + writel(CTRL_RDLVL_GATE_DISABLE, &exynos_dmc->rdlvl_config); - writel(0, &phy0_ctrl->phy_con14); - writel(0, &phy1_ctrl->phy_con14); + writel(0, &exynos_phy0_control->phy_con14); + writel(0, &exynos_phy1_control->phy_con14); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -239,19 +231,20 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); + writel(val, &exynos_phy0_control->phy_con12); + writel(val, &exynos_phy1_control->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(exynos_dmc, DDR_MODE_DDR3); } /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, exynos_dmc); - writel(mem->memcontrol, &dmc->memcontrol); + writel(mem->memcontrol, &exynos_dmc->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); + | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), + &exynos_dmc->concontrol); return 0; } |