diff options
Diffstat (limited to 'src/cpu/samsung/exynos5420/dmc_init_ddr3.c')
-rw-r--r-- | src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index e236e99022..a758433487 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -99,8 +99,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) */ val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); - val |= (0x6 << DA_3_DS_OFFSET) | (0x6 << DA_2_DS_OFFSET) | - (0x6 << DA_1_DS_OFFSET) | (0x6 << DA_0_DS_OFFSET); + val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | + (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); writel(val, &phy0_ctrl->phy_con39); writel(val, &phy1_ctrl->phy_con39); @@ -112,8 +112,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ - writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); - writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); + val = readl(&phy0_ctrl->phy_con14); + val |= mem->phy0_pulld_dqs; + writel(val, &phy0_ctrl->phy_con14); + val = readl(&phy1_ctrl->phy_con14); + val |= mem->phy1_pulld_dqs; + writel(val, &phy1_ctrl->phy_con14); val = MEM_TERM_EN | PHY_TERM_EN; writel(val, &drex0->phycontrol0); @@ -225,8 +229,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) if (mem->gate_leveling_enable) { - setbits_le32(&phy0_ctrl->phy_con0, CTRL_ATGATE); - setbits_le32(&phy1_ctrl->phy_con0, CTRL_ATGATE); + writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); + writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); @@ -236,12 +240,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(val, &phy0_ctrl->phy_con2); writel(val, &phy1_ctrl->phy_con2); - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - val |= BYTE_RDLVL_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); - val = readl(&phy0_ctrl->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); writel(val, &phy0_ctrl->phy_con1); @@ -339,12 +337,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->memcontrol, &drex0->memcontrol); writel(mem->memcontrol, &drex1->memcontrol); - /* Set DMC Concontrol and enable auto-refresh counter */ + /* + * Set DMC Concontrol: Enable auto-refresh counter, provide + * read data fetch cycles and enable DREX auto set powerdown + * for input buffer of I/O in none read memory state. + */ writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), &drex0->concontrol); writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), &drex1->concontrol); /* Enable Clock Gating Control for DMC |