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-rw-r--r--src/cpu/samsung/exynos5420/alternate_cbfs.c79
-rw-r--r--src/cpu/samsung/exynos5420/alternate_cbfs.h6
-rw-r--r--src/cpu/samsung/exynos5420/bootblock.c1
-rw-r--r--src/cpu/samsung/exynos5420/power.h3
4 files changed, 82 insertions, 7 deletions
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c
index 49c9d4c194..416130305a 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c
@@ -22,8 +22,11 @@
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <stdlib.h>
#include <string.h>
+#include <arch/cache.h>
#include <console/console.h>
#include "alternate_cbfs.h"
+#include "cpu.h"
+#include "power.h"
#include "spi.h"
/* This allows USB A-A firmware upload from a compatible host in four parts:
@@ -52,10 +55,13 @@ static int usb_cbfs_open(struct cbfs_media *media)
if (!first_run)
return 0;
+ dcache_mmu_disable();
if (!irom_load_usb()) {
- printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
return -1;
}
+ dcache_mmu_enable();
/*
* We need to trust the host/irom to copy the image to our
@@ -70,6 +76,48 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
}
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / 512;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ *irom_sdmmc_read_blocks_ptr;
+
+ if (!first_run)
+ return 0;
+
+ dcache_mmu_disable();
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+ dcache_mmu_enable();
+
+ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
+ " at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
@@ -90,6 +138,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
@@ -108,8 +169,16 @@ int init_default_cbfs_media(struct cbfs_media *media)
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
- /* TODO: implement SDMMC (and possibly other) boot mode */
-
- return initialize_exynos_spi_cbfs_media(media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+ switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_SPI:
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS,
+ CONFIG_CBFS_CACHE_SIZE);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
+ samsung_get_base_power()->om_stat);
+ return 0;
+ }
}
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h
index 4e9dff9f29..3bb9c760f6 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h
@@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002
u32 * const iram_secondary_base = (u32 *)0x02020018;
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
#if defined(__BOOT_BLOCK__)
/* A small space in IRAM to hold the romstage-only image */
void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index 3df51a7421..1ad75ef493 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -63,7 +63,6 @@ void bootblock_cpu_init(void)
mmu_config_range(0, SRAM_START, DCACHE_OFF);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
- dcache_invalidate_all();
dcache_mmu_enable();
/* For most ARM systems, we have to initialize firmware media source
diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h
index 665e94c197..4efc84efb2 100644
--- a/src/cpu/samsung/exynos5420/power.h
+++ b/src/cpu/samsung/exynos5420/power.h
@@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void);
/* Power Management Unit register map */
struct exynos5_power {
/* Add registers as and when required */
- uint8_t reserved1[0x0400];
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
uint32_t sw_reset; /* 0x0400 */
uint8_t reserved2[0x0304];
uint32_t usb_host_phy_ctrl; /* 0x0708 */