diff options
Diffstat (limited to 'src/cpu/x86/car')
| -rw-r--r-- | src/cpu/x86/car/cache_as_ram.inc | 22 | ||||
| -rw-r--r-- | src/cpu/x86/car/cache_as_ram_post.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/car/copy_and_run.c | 2 |
3 files changed, 13 insertions, 13 deletions
diff --git a/src/cpu/x86/car/cache_as_ram.inc b/src/cpu/x86/car/cache_as_ram.inc index 87ad13d718..4f1ae86af0 100644 --- a/src/cpu/x86/car/cache_as_ram.inc +++ b/src/cpu/x86/car/cache_as_ram.inc @@ -27,7 +27,7 @@ /* disable HyperThreading is done by eswar*/ /* other's is the same as AMD except remove amd specific msr */ -#define CacheSize DCACHE_RAM_SIZE +#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) #include <cpu/x86/mtrr.h> @@ -37,7 +37,7 @@ CacheAsRam: /* hope we can skip the double set for normal part */ -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 // Check whether the processor has HT capability movl $01, %eax @@ -197,29 +197,29 @@ clear_fixed_var_mtrr_out: orl $(0x1<<30),%eax movl %eax, %cr0 -#endif /* USE_FALLBACK_IMAGE == 1*/ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax andl $0x9fffffff,%eax movl %eax, %cr0 -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 /* Read the range with lodsl*/ movl $CacheBase, %esi @@ -277,7 +277,7 @@ clear_fixed_var_mtrr_out: .xout1x: #endif -#endif /*USE_FALLBACK_IMAGE == 1*/ +#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ movl $(CacheBase+CacheSize-4), %eax @@ -314,7 +314,7 @@ var_mtrr_msr: .long 0x20C, 0x20D, 0x20E, 0x20F .long 0x000 /* NULL, end of table */ -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 .align 0x1000 .code16 .global LogicalAP_SIPI @@ -344,5 +344,5 @@ Halt_LogicalAP: hlt jmp Halt_LogicalAP .code32 -#endif /*USE_FALLBACK_IMAGE == 1*/ +#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ .CacheAsRam_out: diff --git a/src/cpu/x86/car/cache_as_ram_post.c b/src/cpu/x86/car/cache_as_ram_post.c index a0b6b17851..f78fb03675 100644 --- a/src/cpu/x86/car/cache_as_ram_post.c +++ b/src/cpu/x86/car/cache_as_ram_post.c @@ -16,7 +16,7 @@ "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "wrmsr\n\t" -#if DCACHE_RAM_SIZE > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 "movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "wrmsr\n\t" #endif diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c index 30b3b7a2f5..7ff63c5e0c 100644 --- a/src/cpu/x86/car/copy_and_run.c +++ b/src/cpu/x86/car/copy_and_run.c @@ -10,7 +10,7 @@ static void copy_and_run(unsigned cpu_reset) if (cpu_reset == 1) cpu_reset = -1; else cpu_reset = 0; -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_ram", cpu_reset); # else cbfs_and_run_core("normal/coreboot_ram", cpu_reset); |