diff options
Diffstat (limited to 'src/cpu/x86/mtrr/earlymtrr.c')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 9561d8dc99..2e31a6e113 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -13,10 +13,10 @@ void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } #if !IS_ENABLED(CONFIG_CACHE_AS_RAM) @@ -36,7 +36,7 @@ const int addr_det = 0; static void do_early_mtrr_init(const unsigned long *mtrr_msrs) { /* Precondition: - * The cache is not enabled in cr0 nor in MTRRdefType_MSR + * The cache is not enabled in cr0 nor in MTRR_DEF_TYPE_MSR * entry32.inc ensures the cache is not enabled in cr0 */ msr_t msr; @@ -65,7 +65,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } @@ -99,7 +99,7 @@ static inline int early_mtrr_init_detected(void) * on both Intel and AMD cpus, at least * according to the documentation. */ - msr = rdmsr(MTRRdefType_MSR); - return msr.lo & MTRRdefTypeEn; + msr = rdmsr(MTRR_DEF_TYPE_MSR); + return msr.lo & MTRR_DEF_TYPE_EN; } #endif |