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-rw-r--r--src/cpu/x86/smm/smmhandler.S2
-rw-r--r--src/cpu/x86/smm/smmrelocate.S3
2 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 484b643017..5d3aae3701 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -108,7 +108,7 @@ smm_handler_start:
/* This is an ugly hack, and we should find a way to read the CPU index
* without relying on the LAPIC ID.
*/
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
/* LAPIC IDs start from 0x10; map that to the proper core index */
subl $0x10, %ecx
#endif
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 6648215e22..21c638ee35 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -24,7 +24,8 @@
/* On AMD's platforms we can set SMBASE by writing an MSR */
#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \
- && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN
+ && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN \
+ && !CONFIG_CPU_AMD_AGESA_FAMILY15_RL
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?