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-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S1
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S1
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S1
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S1
-rw-r--r--src/cpu/intel/microcode/microcode_asm.S2
-rw-r--r--src/cpu/qemu-x86/cache_as_ram_bootblock.S2
6 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 837394c8c9..2c67207154 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -4,6 +4,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+.section .init
.global bootblock_pre_c_entry
.code32
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index cde1ca3d15..0451bb4dd5 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -7,6 +7,7 @@
#define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e
+.section .init
.global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc>
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 71e344778f..887bb22477 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -4,6 +4,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+.section .init
.global bootblock_pre_c_entry
.code32
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 4e36538414..103d9e97f9 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -8,6 +8,7 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
+.section .init
.global bootblock_pre_c_entry
.code32
diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S
index 5173ae5a0c..28705230a2 100644
--- a/src/cpu/intel/microcode/microcode_asm.S
+++ b/src/cpu/intel/microcode/microcode_asm.S
@@ -44,7 +44,7 @@
*/
.code32
-.section .text
+.section .init
.global update_bsp_microcode
update_bsp_microcode:
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 197e0fd8e8..e3a26b0699 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -2,6 +2,8 @@
#include <cpu/x86/post_code.h>
+.section .init, "ax", @progbits
+
.global bootblock_pre_c_entry
bootblock_pre_c_entry: