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-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc23
1 files changed, 0 insertions, 23 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 6702155494..cc52637076 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -17,8 +17,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#include <arch/acpi.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
* and the space used by the reference code. These 2 values combined should
@@ -284,27 +282,6 @@ before_romstage:
post_code(0x3c)
-#if CONFIG_HAVE_ACPI_RESUME
- movl CBMEM_BOOT_MODE, %eax
- cmpl $0x2, %eax // Resume?
- jne __acpi_resume_backup_done
-
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
- * through stage 2. We could keep stuff like stack and heap in high
- * tables memory completely, but that's a wonderful clean up task for
- * another day.
- */
- cld
- movl $CONFIG_RAMBASE, %esi
- movl CBMEM_RESUME_BACKUP, %edi
- movl $HIGH_MEMORY_SAVE >> 2, %ecx
- rep movsl
-
-__acpi_resume_backup_done:
-#endif
-
- post_code(0x3d)
-
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */