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-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c6
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c6
-rw-r--r--src/cpu/amd/pi/00670F00/fixme.c6
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c6
4 files changed, 24 insertions, 0 deletions
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index fcdc9254d9..3be3690227 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -77,4 +77,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
+ MsrReg |= 1 << 11;
+ LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
+ }
}
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index 6770287bca..20353a0a38 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -84,4 +84,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
+ MsrReg |= 1 << 11;
+ LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
+ }
}
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c
index 86f5acf58a..e7d7ba5878 100644
--- a/src/cpu/amd/pi/00670F00/fixme.c
+++ b/src/cpu/amd/pi/00670F00/fixme.c
@@ -88,4 +88,10 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+
+ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
+ MsrReg |= 1 << 11;
+ LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
+ }
}
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index fcdf49815f..674e5c1cb2 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -89,4 +89,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
+ MsrReg |= 1 << 11;
+ LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
+ }
}