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-rw-r--r--src/cpu/amd/car/cache_as_ram_post.c1
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c74
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_msr.h1
-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c20
-rw-r--r--src/cpu/intel/model_f0x/model_f0x_init.c2
-rw-r--r--src/cpu/intel/model_f1x/model_f1x_init.c2
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c2
-rw-r--r--src/cpu/intel/model_f3x/model_f3x_init.c2
-rw-r--r--src/cpu/intel/model_f4x/Config.lb12
-rw-r--r--src/cpu/intel/model_f4x/microcode_MBDF410D.h1024
-rw-r--r--src/cpu/intel/model_f4x/model_f4x_init.c58
-rw-r--r--src/cpu/intel/socket_mPGA604_800Mhz/Config.lb1
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c6
-rw-r--r--src/cpu/x86/mtrr/mtrr.c132
14 files changed, 1245 insertions, 92 deletions
diff --git a/src/cpu/amd/car/cache_as_ram_post.c b/src/cpu/amd/car/cache_as_ram_post.c
index 66ca9fdf96..6a129b258a 100644
--- a/src/cpu/amd/car/cache_as_ram_post.c
+++ b/src/cpu/amd/car/cache_as_ram_post.c
@@ -1,4 +1,5 @@
/* by yhlu 6.2005 */
+/* be warned, this file will be used other cores and core0/node0 */
__asm__ volatile (
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index b75025b4c8..3c526e78ca 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -192,6 +192,7 @@ static void init_ecc_memory(unsigned node_id)
/* If ecc support is not enabled don't touch memory */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl & DCL_DimmEccEn)) {
+ printk_debug("ECC Disabled\n");
return;
}
@@ -226,7 +227,9 @@ static void init_ecc_memory(unsigned node_id)
disable_lapic();
/* Walk through 2M chunks and zero them */
- for(basek = begink; basek < endk; basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
+ for(basek = begink; basek < endk;
+ basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
+ {
unsigned long limitk;
unsigned long size;
void *addr;
@@ -255,12 +258,13 @@ static void init_ecc_memory(unsigned node_id)
}
size = (limitk - basek) << 10;
addr = map_2M_page(basek >> 11);
- addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
if (addr == MAPPING_ERROR) {
+ printk_err("Cannot map page: %x\n", basek >> 11);
continue;
}
/* clear memory 2M (limitk - basek) */
+ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
clear_memory(addr, size);
}
/* Restore the normal state */
@@ -319,19 +323,16 @@ static inline void k8_errata(void)
}
wrmsr(NB_CFG_MSR, msr);
}
-// AMD_D0_SUPPORT
+
+ /* Erratum 97 ... */
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
- /* D0 later don't need it */
- /* Erratum 97 ... */
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= 1 << 3;
wrmsr_amd(DC_CFG_MSR, msr);
- }
-
-//AMD_D0_SUPPORT
- if(is_cpu_pre_d0()) {
- /*D0 later don't need it */
- /* Erratum 94 ... */
+ }
+
+ /* Erratum 94 ... */
+ if (is_cpu_pre_d0()) {
msr = rdmsr_amd(IC_CFG_MSR);
msr.lo |= 1 << 11;
wrmsr_amd(IC_CFG_MSR, msr);
@@ -339,37 +340,51 @@ static inline void k8_errata(void)
/* Erratum 91 prefetch miss is handled in the kernel */
-//AMD_D0_SUPPORT
+ /* Erratum 106 ... */
+ msr = rdmsr_amd(LS_CFG_MSR);
+ msr.lo |= 1 << 25;
+ wrmsr_amd(LS_CFG_MSR, msr);
+
+ /* Erratum 107 ... */
+ msr = rdmsr_amd(BU_CFG_MSR);
+ msr.hi |= 1 << (43 - 32);
+ wrmsr_amd(BU_CFG_MSR, msr);
+
if(is_cpu_d0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
- }
+ }
-//AMD_E0_SUPPORT
- if(!is_cpu_pre_e0()) {
- /* Erratum 110 ...*/
+ if (!is_cpu_pre_e0()) {
+ /* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |=1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+
+ /* Erratum 122 */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= 1 << 6;
+ wrmsr(HWCR_MSR, msr);
+
}
void model_fxx_init(device_t dev)
{
unsigned long i;
msr_t msr;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
struct node_core_id id;
- unsigned siblings;
+ unsigned siblings;
id.coreid=0;
#else
unsigned nodeid;
#endif
/* Turn on caching if we haven't already */
- x86_enable_cache();
+ x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
@@ -386,11 +401,12 @@ void model_fxx_init(device_t dev)
enable_cache();
-#if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS == 1
siblings = cpuid_ecx(0x80000008) & 0xff;
-// id = get_node_core_id((!is_cpu_pre_e0())? read_nb_cfg_54():0);
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
if(siblings>0) {
@@ -407,24 +423,24 @@ void model_fxx_init(device_t dev)
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+
/* Is this a bad location? In particular can another node prefecth
* data from this node before we have initialized it?
*/
- if(id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core0
+ if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
#else
- /* For now there is a 1-1 mapping between node_id and cpu_id */
- nodeid = lapicid() & 0x7;
+ /* Is this a bad location? In particular can another node prefecth
+ * data from this node before we have initialized it?
+ */
+ nodeid = lapicid() & 0xf;
init_ecc_memory(nodeid);
#endif
-
- /* Enable the local cpu apics */
- setup_lapic();
#if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
/* Start up my cpu siblings */
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
#endif
+
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/model_fxx/model_fxx_msr.h b/src/cpu/amd/model_fxx/model_fxx_msr.h
index c8d57bee1a..b4795cbbb2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_msr.h
+++ b/src/cpu/amd/model_fxx/model_fxx_msr.h
@@ -3,6 +3,7 @@
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
+#define LS_CFG_MSR 0xC0011020
#define IC_CFG_MSR 0xC0011021
#define DC_CFG_MSR 0xC0011022
#define BU_CFG_MSR 0xC0011023
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index de4ed988c2..e57bb3bec7 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -96,26 +96,32 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
return;
}
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
- start_mtrr, last_mtrr);
+ start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
}
+extern void enable_fixed_mtrr(void);
+
void amd_setup_mtrrs(void)
{
+ unsigned long address_bits;
struct mem_state state;
unsigned long i;
msr_t msr;
+
/* Enable the access to AMD RdDram and WrDram extension bits */
+ disable_cache();
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr);
+ enable_cache();
printk_debug("\n");
/* Initialized the fixed_mtrrs to uncached */
printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
- 0, NUM_FIXED_RANGES);
+ 0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
/* Except for the PCI MMIO hole just before 4GB there are no
@@ -127,6 +133,7 @@ void amd_setup_mtrrs(void)
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_fixed_mtrr_resource, &state);
printk_debug("DONE fixed MTRRs\n");
+
if (state.mmio_basek > state.tomk) {
state.mmio_basek = state.tomk;
}
@@ -164,10 +171,17 @@ void amd_setup_mtrrs(void)
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr);
+ enable_fixed_mtrr();
+
enable_cache();
+ /* FIXME we should probably query the cpu for this
+ * but so far this is all any recent AMD cpu has supported.
+ */
+ address_bits = 40;
+
/* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory.
*/
- x86_setup_mtrrs();
+ x86_setup_var_mtrrs(address_bits);
}
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 55504a1049..474d025799 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -30,7 +30,7 @@ static void model_f0x_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 53cee4fe68..42dff1e276 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -30,7 +30,7 @@ static void model_f1x_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 4f69d81d2a..f019ea4473 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -34,7 +34,7 @@ static void model_f2x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index a89e7d1782..20b8518c7c 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb
new file mode 100644
index 0000000000..66f6ceb00f
--- /dev/null
+++ b/src/cpu/intel/model_f4x/Config.lb
@@ -0,0 +1,12 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_f4x_init.o
diff --git a/src/cpu/intel/model_f4x/microcode_MBDF410D.h b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
new file mode 100644
index 0000000000..9266ce5c34
--- /dev/null
+++ b/src/cpu/intel/model_f4x/microcode_MBDF410D.h
@@ -0,0 +1,1024 @@
+0x00000001, /* Header Version */
+0x0000000d, /* Patch ID */
+0x11032004, /* DATE */
+0x00000f41, /* CPUID */
+0xa3430d74, /* Checksum */
+0x00000001, /* Loader Version */
+0x000000bd, /* Platform ID */
+0x00000fd0, /* Data size */
+0x00001000, /* Total size */
+0x00000000, /* reserved */
+0x00000000, /* reserved */
+0x00000000, /* reserved */
+0x23869663,
+0x00e8d132,
+0xc1efa329,
+0x20662968,
+0xb833cad6,
+0x78012780,
+0x0971cf44,
+0xda1410ae,
+0xece61219,
+0x5ec0a10c,
+0x5a1c529c,
+0x9b5e4fac,
+0x35fee068,
+0x24bb3539,
+0xa6c23421,
+0x0309a01d,
+0x80331c7b,
+0x960d5da2,
+0x56d31115,
+0xdaadb98b,
+0x8d5c0ca8,
+0xc1fc4f86,
+0xef6ee956,
+0x512c9483,
+0x08a9c125,
+0x03b95162,
+0x6499668c,
+0x25e15127,
+0xfb4f0f0b,
+0x10d1b2c3,
+0x542be728,
+0xa0f11cc9,
+0xa5bc6bd2,
+0xf3b7cc86,
+0xe4a91466,
+0x41eceee1,
+0x5beb249b,
+0x6ab82791,
+0x2c5a86ac,
+0x90c2865d,
+0x4702c4a5,
+0xbddad5f1,
+0xb2e224fb,
+0x0ffb50d3,
+0x13c6933c,
+0xc573b9df,
+0x908510f6,
+0xca6f3a9e,
+0x2049f489,
+0xe20b8848,
+0xfd659d6e,
+0xc9afd397,
+0x1432aa70,
+0x62c3e20c,
+0xee6dda59,
+0xe8601135,
+0xa9e30f8e,
+0x691b59e5,
+0x0446816b,
+0xd63a3f0c,
+0x5d1b9d99,
+0xfe8d9637,
+0xee61a0a4,
+0xeeae5aa0,
+0x709d78e6,
+0x5468e7fb,
+0x7e0f2dc3,
+0x632591e1,
+0x990864bb,
+0x413a220b,
+0x5285bdcd,
+0xb7323fa6,
+0xfe0098ce,
+0xd05d24b2,
+0x51ee2e1e,
+0x0078c207,
+0x9d1e1514,
+0x1be23c59,
+0xa80398e4,
+0xe0fa94c8,
+0x2b2f841e,
+0x21144f67,
+0x0a6a1413,
+0xfa30499a,
+0xba49558e,
+0x1607d767,
+0xebd70987,
+0x00cb016d,
+0xac1de18a,
+0xfcde8566,
+0x23f51d05,
+0xb7368509,
+0x9b1947fd,
+0x0d0d3c22,
+0xfbeab67d,
+0xfc963120,
+0x0aeae56b,
+0x0dbe2aeb,
+0x6d4ba825,
+0xab4b8dae,
+0x23bbe7a0,
+0x53d38f2e,
+0x6ee7bed3,
+0x39869966,
+0x8e36076d,
+0x410dca57,
+0x133c4861,
+0xcc2920d0,
+0xb1cfc172,
+0xd3c2e94b,
+0x8cdb7550,
+0xcb14be86,
+0x1c72bb42,
+0x469a6066,
+0x912f65eb,
+0x173ac7b9,
+0xfa02afca,
+0x23fc44f2,
+0xbbf0c89f,
+0xa018ba5f,
+0x950654d1,
+0x1b6d7652,
+0xb2a04767,
+0x86630316,
+0xff3fd7b3,
+0x9c9b3aba,
+0xb7d6115b,
+0x7c7a354c,
+0x1761b195,
+0xc54b49dd,
+0x2e0f5f20,
+0xaf1e90b2,
+0x07056032,
+0x46ccdd94,
+0xcc751ec5,
+0x4774af8a,
+0x24a3dba1,
+0xa388bccc,
+0xacd1c25a,
+0x4ee406c1,
+0x9861931a,
+0x5bae36e2,
+0xafc6e087,
+0x8d36cd1b,
+0x25f894d1,
+0xd749fdaa,
+0x3cef917d,
+0xb85440c2,
+0x4d22a2bf,
+0x19703ee4,
+0xa5fd9e1e,
+0x76062779,
+0x14031f62,
+0x6e309271,
+0x55476f65,
+0xb4fd2411,
+0x554882db,
+0xee9d4d38,
+0x57faf730,
+0x730e0285,
+0xb882d382,
+0xc156852d,
+0xf2db8f7a,
+0xea52f3e4,
+0x323430d1,
+0x51ea5fe9,
+0x0929d601,
+0x8e6740cf,
+0x69c456e1,
+0xd9e2f5c1,
+0x0124bf3b,
+0x0220f415,
+0xfbe91365,
+0x2bc82d06,
+0x0a31f25c,
+0xbeaf32af,
+0x3c2175b7,
+0xe8f67a0e,
+0x177bb8fa,
+0x33b86eb3,
+0x3ba0e579,
+0x368fc48b,
+0xe6665da8,
+0x688bfd43,
+0x48448000,
+0xc5c99d34,
+0xab99cfeb,
+0x1ce9c58d,
+0x773ae448,
+0x3534d849,
+0x6d86470f,
+0x306db8d0,
+0x550c15ff,
+0x7a2c439a,
+0xe6f1b78f,
+0x0bf4cdd7,
+0xfbcab3d7,
+0x402e87ec,
+0xf4ee5874,
+0xc03c70d9,
+0x3b9ed9e6,
+0x04ef67e0,
+0xd04ae924,
+0xf6845607,
+0x5e58c954,
+0xc2fdf283,
+0xc558ae4e,
+0x8300ece1,
+0x7bbaea80,
+0xc5d0b0f1,
+0xfc9e8004,
+0xfcea494a,
+0x04f4eb47,
+0x129f505d,
+0xccbae019,
+0x59c0616f,
+0xaaba53a8,
+0x19d8a002,
+0x361fb171,
+0x00c4aee2,
+0x6bb0dfb0,
+0xc03d6b9a,
+0xabaed6fb,
+0xa23c48fe,
+0x50866e98,
+0xbb499854,
+0xb5730aad,
+0xbe89d93c,
+0xe6d35886,
+0x7ae05c20,
+0xc2708cbd,
+0xf8f18059,
+0xf492c48e,
+0x14121e3d,
+0x9e9dc5a7,
+0xafa3ef3a,
+0x17535114,
+0x08296547,
+0xe1ab5d3c,
+0x2e51d954,
+0x0e6953db,
+0xde0ea136,
+0xd1f37944,
+0x3074f7ed,
+0x3b196093,
+0x0efb3b56,
+0x3b904c2c,
+0xcef179ee,
+0xc854e7f5,
+0x48aa28ce,
+0x1c0cb17e,
+0xae4236b2,
+0x87c5dc18,
+0x7832ec05,
+0xc4212949,
+0xca5a40d2,
+0x8e8f431d,
+0x328df52b,
+0xe4dd2524,
+0x7b8ae78a,
+0x17ba24a3,
+0x25eb59d5,
+0x1a341b63,
+0x45f1e3f2,
+0x0e2d9cf8,
+0xa66c17e8,
+0x515bc934,
+0xfea866d3,
+0xd149deac,
+0x740a7cf5,
+0x2f47375b,
+0xa5fdd0c4,
+0xd8965720,
+0x4ecefd2f,
+0x1916443a,
+0x984995a9,
+0x7b919733,
+0x80f02747,
+0x30fe0d17,
+0x65a68843,
+0xdb0931ad,
+0x0929b113,
+0x1bd4cc0c,
+0x7b2f63fd,
+0x6238656c,
+0x8a1badab,
+0x6565a869,
+0xca48cce2,
+0x7ff6bdc3,
+0x772305d4,
+0x376639d3,
+0x56ed9f11,
+0x75e17cef,
+0x7dffbcf4,
+0xfbafb077,
+0x932aed24,
+0x8b04ebf4,
+0x768ac85f,
+0xb54a99f9,
+0xd4fdf692,
+0x43b09d0a,
+0x32d81423,
+0xcb2a74e6,
+0x59f40d29,
+0x6392b933,
+0x7a3bc72c,
+0xfa647af0,
+0x2c28e15f,
+0xa724e1b0,
+0x6174f8f6,
+0x651672ab,
+0xd8eb376a,
+0x61d18571,
+0xa9bab242,
+0x2ba20ac2,
+0x332c20a9,
+0x21e71331,
+0x7ba9dbe4,
+0x1e61e44d,
+0x07ee9579,
+0xd1846f7a,
+0xca29125b,
+0x11958b89,
+0xb6fe5a2b,
+0x249991b4,
+0x5f28c005,
+0x0b909d87,
+0x673159ab,
+0xf25d3b1a,
+0x2a7f0d31,
+0x2e741145,
+0x60c1525d,
+0x7a2996a7,
+0x5051ead4,
+0xb9473e57,
+0x7c5f9d0e,
+0x51584719,
+0xa25c2246,
+0xceec4103,
+0x813e68be,
+0xabf2eed8,
+0x4fb4988f,
+0x678fba46,
+0x801b82e1,
+0x7fc428dc,
+0xa30bf423,
+0xd1dc03db,
+0x65d1f1fb,
+0xfea39d25,
+0x7b8cfad4,
+0x7eda42af,
+0x4c7cb670,
+0x1ac54e69,
+0x6ecd00ae,
+0x2ff34b4e,
+0x0f7c1999,
+0x14713cb0,
+0x3942aea8,
+0x07832b5c,
+0x5cd3fa0c,
+0x918b4916,
+0xe9420e66,
+0x8bd0f43c,
+0x28e79a91,
+0x999c89a3,
+0x59da832c,
+0x3dd8cb18,
+0x67deb7fe,
+0xa4f503bb,
+0x77f8114f,
+0xe732a72b,
+0x7e8b8835,
+0x10192856,
+0x54da048f,
+0x8ea0f6cd,
+0x722ba57f,
+0x133ad6fc,
+0x7d486fb3,
+0x27764f83,
+0x8c0dff5f,
+0x9f137e77,
+0x5d6b4057,
+0xeef4eee0,
+0xb0e0e900,
+0xf37b72f1,
+0xec1b84f5,
+0x0a454136,
+0xc23a91a3,
+0x0ab3bae8,
+0x715496f9,
+0xc1082181,
+0xccf9217f,
+0x5213635d,
+0x2e29ab5b,
+0xb4574eef,
+0x2bc2fea8,
+0x1ee67ef8,
+0xd567c2b8,
+0xfc19ef2c,
+0xe19af740,
+0x28a28944,
+0x836be662,
+0xb0080f12,
+0xd6f61914,
+0x33c85c03,
+0x326e680f,
+0x87b45aa5,
+0xad7c015b,
+0x63e312a9,
+0x65fb08cf,
+0x5fca6d27,
+0x7b57bef5,
+0x466fa276,
+0x56c21f72,
+0x38fb8f1d,
+0xc1966d08,
+0x15d4c28b,
+0xeec1eade,
+0x905f5218,
+0x5be29b59,
+0xb64aa150,
+0xc8994548,
+0xe4bfb038,
+0xd63e54cf,
+0x98469c03,
+0xb28e3b7b,
+0xf852cae3,
+0xc76b8b09,
+0x16810021,
+0x8ea0bfec,
+0xdfc083e5,
+0x884c8453,
+0x908a80f2,
+0xb6d91870,
+0x56ad6422,
+0x05174668,
+0x380d8035,
+0xeef37603,
+0x38ff195e,
+0x44898288,
+0xb300620f,
+0xa814ec47,
+0xa58d3007,
+0x7d4536f5,
+0x2dfc2f4d,
+0xfa2ae308,
+0x24d4799f,
+0x1423df15,
+0x82dc572b,
+0xa3141ca3,
+0xa1210bb1,
+0xb7eecdc4,
+0x5d9ac524,
+0xb8f4b3fb,
+0x6cd8f8a8,
+0x0e745c45,
+0xb0041dbe,
+0x6ee22101,
+0xc9fb746b,
+0x69909b4d,
+0x9e63a31c,
+0xbc627065,
+0x6b24225b,
+0x1d2b80b1,
+0x4c08e46b,
+0x1f78a68c,
+0x75bc0a34,
+0x74d23ab8,
+0xb16d2786,
+0xfbb6fa5f,
+0xc9bbf303,
+0x69ebae66,
+0xcfa4bf29,
+0xaa69d19e,
+0x5d965c81,
+0x7cebac23,
+0x030b7aca,
+0x7983efba,
+0x03babdb7,
+0xd9d7a8bb,
+0xa939d7e1,
+0x6913d42f,
+0xfce3f3b5,
+0xb9d2a26b,
+0x32e614b2,
+0xbbb00851,
+0x4313ca42,
+0xe17a6d39,
+0x5b9f0631,
+0x90569ece,
+0xf980f983,
+0x13eb7233,
+0xc8da9166,
+0x60dbe5fc,
+0x4621997a,
+0xccd2a527,
+0x061180aa,
+0xa92467da,
+0x3dc79eef,
+0x39f31e91,
+0x9e45191c,
+0x7dcba672,
+0xfc23a8b8,
+0x1a773f6a,
+0x6fc6fa46,
+0x46b50e14,
+0x514bd261,
+0xe6cc3574,
+0x5a88dea2,
+0x9121d758,
+0x7f39e3bf,
+0x9ab043b6,
+0xc1007d0c,
+0xc3c3ff8e,
+0x08411386,
+0x0bd529d7,
+0xcaa9a1d8,
+0x27b19be2,
+0x95703f7e,
+0x44ab493a,
+0xcf1fc404,
+0x3f34062d,
+0xa56d454b,
+0x9464f996,
+0x1346eadf,
+0xdd6e6895,
+0x27b5ba10,
+0xb84c1d0c,
+0x5fa57ca4,
+0xad052de8,
+0xf5b4a3ae,
+0x6a61144d,
+0x48c00092,
+0x4897fad0,
+0x90b7b116,
+0xcdf29b2c,
+0xa41aac9a,
+0x147d09f7,
+0xebf3615d,
+0xb3ddf0b0,
+0xc8edc675,
+0x43cbf71b,
+0xfa0a0b5c,
+0xe0b63692,
+0x6c5870a9,
+0xe0b37be9,
+0xb16acc39,
+0xc55aed8c,
+0xd34fb041,
+0x24735885,
+0x0fff6e94,
+0x834181e8,
+0x56671872,
+0xb3f2e29b,
+0xfa383cd3,
+0xe585e5b6,
+0xa40cb894,
+0x1fe8376a,
+0xf794c60a,
+0xa3efdb18,
+0x0df1f1b4,
+0x54230798,
+0xd2a8ba49,
+0x349ce466,
+0xcbff13b4,
+0x71a63418,
+0x728ae615,
+0xf7c4f811,
+0x0dd072d8,
+0x9aa6fac7,
+0xa44210d0,
+0x2a1a85bf,
+0x1e18a8c6,
+0xbe2bb680,
+0xfed00f0e,
+0x2acc1b4b,
+0x4f049f6f,
+0x6f5aeec1,
+0x2db8f7b4,
+0xd61041a2,
+0x5cc7c861,
+0xb6ed3676,
+0x02aef566,
+0x2b6d41c8,
+0xaba9296e,
+0xf7b032cd,
+0xc290e538,
+0x584ad0f9,
+0x95289bc7,
+0x49b428b8,
+0x84bb41d4,
+0xdf0fcf91,
+0x9bd712a9,
+0xc6f730e1,
+0xe28b78d4,
+0x45b0480d,
+0x29d344bf,
+0xcd0101bb,
+0x18561b59,
+0xcfa84f65,
+0x76e798eb,
+0xac73f8af,
+0x71fe2488,
+0x207dd75d,
+0x198130e5,
+0x3604d44d,
+0xd895dc9b,
+0xf55fe7e2,
+0x4fed2e51,
+0xf434e20a,
+0x7c3204e8,
+0x4d653a59,
+0x6652a556,
+0x8713f1e2,
+0xa69dea42,
+0x2fd0ee37,
+0xe7617993,
+0xc0791c80,
+0x57e14435,
+0x87fcad6e,
+0x96505f56,
+0x838e7a38,
+0x78b228ab,
+0x84411d16,
+0x0b4e1d87,
+0x21f17d96,
+0x72021b3c,
+0xe69f4784,
+0x324fb9b4,
+0x041c7459,
+0x500ffe39,
+0x6e561c0f,
+0xadaf6fd7,
+0x0c91509f,
+0x8be04594,
+0x6a5ead5a,
+0x313c9f9d,
+0xe4754919,
+0x63d7cebc,
+0x02d0ad32,
+0x2dc3cdb7,
+0xd9b2e421,
+0xa1ad018c,
+0xd954f545,
+0x9f3871b2,
+0xf8a9a4a9,
+0x4cdc558d,
+0x300c9685,
+0x639f4b78,
+0x2181680d,
+0xb96442d6,
+0x7821a1a2,
+0x174a9e5b,
+0x79320590,
+0xf580c60c,
+0xba8539ce,
+0x59905669,
+0xc6f39c94,
+0xb57cc9bf,
+0xc2f7ad76,
+0x8d9ebc2d,
+0x6c33e47f,
+0x29294c84,
+0x49a2bef6,
+0x8aa6f79b,
+0x809f0eb5,
+0x3691aa7f,
+0xcf4b0e8f,
+0xec44f802,
+0x16bf83a7,
+0x82c00d36,
+0xa99071b1,
+0xe3815c76,
+0xc0835331,
+0xc794c55f,
+0x041b44af,
+0x2fa75171,
+0x985bd852,
+0xc4391e66,
+0x7bf08eaf,
+0x2b826882,
+0xfb8834dc,
+0x9128681e,
+0x6a2cb9ef,
+0x6d1d20f9,
+0x9f90ee4d,
+0xc48c3ee3,
+0xdd063585,
+0x82454044,
+0xf7077f1a,
+0x47e6e556,
+0xd803f7dd,
+0x98f67f71,
+0x9089e4ac,
+0xe7f09610,
+0xa9e3f93b,
+0x420c1550,
+0xc01f7710,
+0x0905da5e,
+0x02d71f99,
+0xbf36b473,
+0x50a96e32,
+0x2dedb8b9,
+0x9e3051a2,
+0x84c023c4,
+0xd43073b1,
+0x74f23fbb,
+0xd42a4487,
+0x266dfc42,
+0x6be0acdf,
+0xa986294c,
+0x3ee65aa8,
+0x19c1cf4f,
+0x2fdf8308,
+0xa6a64910,
+0xc3fa82e8,
+0x2943c8b8,
+0xf1a60b7b,
+0x4cc9ea04,
+0x3cc95270,
+0x054a8d2b,
+0xae7a4525,
+0x2e2abb62,
+0x24b9522b,
+0xb95a6668,
+0xad8c237d,
+0x1ea73bf8,
+0xff33f0d6,
+0x772a16a3,
+0xfefabdc4,
+0xb181234c,
+0xab59fb47,
+0x96f2c987,
+0xff0d4f54,
+0x6e938aba,
+0x727e6266,
+0xea0d851f,
+0x2ced3474,
+0x8c2e7718,
+0xa576c375,
+0xc97addeb,
+0x2f46a635,
+0xdb669986,
+0xa4333f93,
+0x7042c2c6,
+0x419fda5f,
+0x95b8aa3f,
+0x6ad05dc8,
+0x8b90655a,
+0xd8c77947,
+0x20508480,
+0xfa3cdf6b,
+0xdbb44af2,
+0x235941d0,
+0x3154c107,
+0x566bc32a,
+0x426fb2cd,
+0xd2010afa,
+0xe2775abe,
+0x6f543a20,
+0x2c626450,
+0x34f193f4,
+0x37ac5908,
+0x58a7eca6,
+0xc4859881,
+0x183393ff,
+0xab9abed9,
+0xde947d21,
+0xffec2b7d,
+0xb21b8788,
+0xb527117f,
+0x199dffe5,
+0xd7ebe4e6,
+0xc89a72b0,
+0x91cc3042,
+0x91bd3463,
+0x736e6f4f,
+0x0cc208bc,
+0x029f21cb,
+0x3f204418,
+0x050db787,
+0x71b56562,
+0xaf07f08f,
+0xaca4701f,
+0x88d4f2f8,
+0xf98fe016,
+0xb47672c6,
+0xed601c94,
+0x285db8b8,
+0x28a81c19,
+0x9e2763ce,
+0xe39741c0,
+0xcd9fce6d,
+0xe9917796,
+0xfdd3ebaf,
+0x99dcb253,
+0xe9aa0db4,
+0x3a65c0b0,
+0xb39c61fb,
+0x1f413c5e,
+0x60576c8c,
+0x48d6df34,
+0x0cbca786,
+0x4caff4b7,
+0x8473e181,
+0x36eed747,
+0x82f486af,
+0x79f02eed,
+0xab6886ed,
+0x06aef911,
+0xad42a654,
+0x5471c813,
+0xc8bbe710,
+0xfc65fd97,
+0x60f467af,
+0xf56b71d8,
+0xc1d6f193,
+0x3a1c42bf,
+0x46ce3b78,
+0x39472626,
+0x04dc137e,
+0xb48dc9dd,
+0xdfd27741,
+0x4718e5a2,
+0x00ba4728,
+0x855b661f,
+0x6d98577f,
+0xc3b48131,
+0x2b0384c1,
+0x8af572fe,
+0x760aa4e3,
+0x2f5b53fb,
+0xb9234297,
+0x401b47f5,
+0x44237cc0,
+0x2f7205f4,
+0x19b63c6e,
+0x7c375e6b,
+0x152c42d8,
+0x603731c7,
+0xc67601fb,
+0xa5d4826c,
+0x9068966f,
+0x864fe2f9,
+0xb37311d9,
+0xe6e4a34a,
+0xd46ee161,
+0xecd76c4a,
+0x90d0328a,
+0x4865b540,
+0xd2e13982,
+0x7e3925f4,
+0xc850a518,
+0x63bffcce,
+0x7cdb918f,
+0xcd8786d3,
+0xcf83df01,
+0x27122e50,
+0x0f014b76,
+0xde1485d7,
+0xa6ff496f,
+0xed0812f7,
+0x34efe965,
+0x12a63465,
+0xb83d9f77,
+0x040efa2e,
+0x4ac576d1,
+0x185430dd,
+0xb4271745,
+0x9bb58be2,
+0x7f55d4bb,
+0xca7dae0b,
+0x0bfe5147,
+0x4a9ade45,
+0x20bdc545,
+0xdf66689d,
+0x22e29493,
+0x31763c1f,
+0x2d021cd2,
+0x06286428,
+0xc7bba5d4,
+0x6bc42a0e,
+0x1c987082,
+0xd6c6c2f9,
+0x2c1ecdd0,
+0x84946249,
+0x42c1c41b,
+0x6d949e60,
+0x9dbb1571,
+0xf6b1df68,
+0x0705ae1a,
+0xa1ec5add,
+0x7e94d7c8,
+0x7d4d451d,
+0xd53c13d4,
+0x0204877b,
+0x0f0e44e0,
+0xdf25570f,
+0xd2a9adaf,
+0x556aeacf,
+0x2f985a30,
+0x706c42c6,
+0x2d5a76a5,
+0xdc428213,
+0xdf2864a2,
+0x0f6788a9,
+0xc764d3a6,
+0x9211d0ca,
+0x59e3f5cc,
+0xd31fd5b6,
+0xfa8b535b,
+0x2cac74bb,
+0xc43f36b2,
+0xf83b5bac,
+0x96c255bf,
+0x45915993,
+0x657d751a,
+0x9b86b994,
+0xddab62fd,
+0x1b6ac108,
+0x559073c9,
+0xe60a0bda,
+0xd65df6de,
+0x41f7e5d4,
+0x825a5701,
+0x377307b6,
+0x08176ce6,
+0x7a8a2c4a,
+0xd7ecb869,
+0x02710179,
+0x75e7517c,
+0xdfaf2c82,
+0x67590275,
+0x6ad621af,
+0xaedaa35c,
+0xfa8fbee3,
+0x9e5dda5f,
+0x09f571fa,
+0xe358dbfe,
+0x1b3300f1,
+0x05567c6b,
+0x5a9d335f,
+0x215114f8,
+0xd5744f0a,
+0x78ecc142,
+0x9b5f60b8,
+0x30f8fed2,
+0x5c013696,
+0x675c84de,
+0xdb50bbcc,
+0x7c504a4e,
+0x3ffc5fda,
+0x24b2c30a,
+0xac00d64a,
+0x97832b52,
+0xb34d9975,
+0x93c6cb4e,
+0x471bfcae,
+0xaabbb6d8,
+0x0bc6a5e5,
+0x6875c630,
+0xf4cce30c,
+0xdab0d64b,
+0x29aba8b9,
+0xe34b3cde,
+0x8654e470,
+0x2c5041f7,
+0xdcf5eff9,
+0x26a88f84,
+0x9d374761,
+0xefa60ac4,
+0xdf0d0fd3,
+0x72e37e59,
+0xa76d26e1,
+0x3ffe2408,
+0x13ecf42d,
+0x46de7cba,
+0x43330219,
+0xc2536a31,
+0xa69c4729,
+0x114990f8,
+0x3f08ed00,
+0xeaa05cae,
+0x08f06e57,
+0x30f4a62f,
+0x963a7557,
+0x631fb75f,
+0x1344a74b,
+0x1e80cef5,
+0x8a4f86dd,
+0x0f7f1c62,
+0xfe9f5809,
+0x710d86de,
+0x8939283d,
+0x19403076,
+0x26ce286b,
+0x6baaf798,
+0xbc1d2808,
+0xea980728,
+0x72288979,
+0x7c92be68,
+0x0a7af91b,
+0x7bb8059b,
+0xe7eca99c,
+0xd3a8819f,
+0xb9182916,
+0x0c48ba1e,
+0xb6aaf63b,
+0x10a740a6,
+0x0aa2e4e7,
+0x0bf27e94,
+0x6d266f86,
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
new file mode 100644
index 0000000000..649638670d
--- /dev/null
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -0,0 +1,58 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static uint32_t microcode_updates[] = {
+ /* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+#include "microcode_MBDF410D.h"
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_f4x_init(device_t cpu)
+{
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+ x86_setup_mtrrs(36);
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_f4x_init,
+};
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */
+ { 0, 0 },
+};
+
+static struct cpu_driver model_f4x __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
index 0b794338a2..2637c86594 100644
--- a/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
+++ b/src/cpu/intel/socket_mPGA604_800Mhz/Config.lb
@@ -1,3 +1,4 @@
config chip.h
object socket_mPGA604_800Mhz.o
dir /cpu/intel/model_f3x
+dir /cpu/intel/model_f4x
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index c435b2edd5..105f7c49df 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -37,8 +37,8 @@ static void disable_var_mtrr(unsigned reg)
wrmsr(MTRRphysMask_MSR(reg), zero);
}
-static void set_var_mtrr(unsigned reg, unsigned base, unsigned size,
- unsigned type)
+static void set_var_mtrr(
+ unsigned reg, unsigned base, unsigned size, unsigned type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
@@ -76,7 +76,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
msr.lo = 0;
msr.hi = 0;
unsigned long msr_nr;
- for (msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
+ for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
wrmsr(msr_nr, msr);
}
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 59f9ca1e91..1226713cf5 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -22,9 +22,14 @@
*
* Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
*/
+
/*
- 2005.1 yhlu add NC support to spare mtrrs for 64G memory stored
+ 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
+ 2005.6 Eric add address bit in x86_setup_mtrrs
+ 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
+ for AMD, it will not use x86_setup_fixed_mtrrs
*/
+
#include <stddef.h>
#include <console/console.h>
#include <device/device.h>
@@ -32,19 +37,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
-#warning "FIXME I do not properly handle address more than 36 physical address bits"
-
-//#define k8 0
-#define k8 1
-
-#if k8
-# define ADDRESS_BITS 40
-#else
-# define ADDRESS_BITS 36
-#endif
-#define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
-#define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
-
static unsigned int mtrr_msr[] = {
MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
@@ -52,7 +44,7 @@ static unsigned int mtrr_msr[] = {
};
-static void enable_fixed_mtrr(void)
+void enable_fixed_mtrr(void)
{
msr_t msr;
@@ -71,21 +63,26 @@ static void enable_var_mtrr(void)
}
/* setting variable mtrr, comes from linux kernel source */
-static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
+static void set_var_mtrr(
+ unsigned int reg, unsigned long basek, unsigned long sizek,
+ unsigned char type, unsigned address_bits)
{
msr_t base, mask;
+ unsigned address_mask_high;
+
+ address_mask_high = ((1u << (address_bits - 32u)) - 1u);
base.hi = basek >> 22;
base.lo = basek << 10;
- //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
+ printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
if (sizek < 4*1024*1024) {
- mask.hi = ADDRESS_MASK_HIGH;
+ mask.hi = address_mask_high;
mask.lo = ~((sizek << 10) -1);
}
else {
- mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
+ mask.hi = address_mask_high & (~((sizek >> 22) -1));
mask.lo = 0;
}
@@ -219,7 +216,7 @@ static unsigned fixed_mtrr_index(unsigned long addrk)
static unsigned int range_to_mtrr(unsigned int reg,
unsigned long range_startk, unsigned long range_sizek,
- unsigned long next_range_startk, unsigned char type)
+ unsigned long next_range_startk, unsigned char type, unsigned address_bits)
{
if (!range_sizek || (reg >= BIOS_MTRRS)) {
return reg;
@@ -235,11 +232,11 @@ static unsigned int range_to_mtrr(unsigned int reg,
}
sizek = 1 << align;
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
- reg, range_startk >>10, sizek >> 10,
- (type==MTRR_TYPE_UNCACHEABLE) ? "NC" :
- ((type==MTRR_TYPE_WRBACK) ? "WB" : "Other")
+ reg, range_startk >>10, sizek >> 10,
+ (type==MTRR_TYPE_UNCACHEABLE)?"UC":
+ ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
);
- set_var_mtrr(reg++, range_startk, sizek, type);
+ set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
range_startk += sizek;
range_sizek -= sizek;
if (reg >= BIOS_MTRRS)
@@ -279,6 +276,7 @@ struct var_mtrr_state {
unsigned long range_startk, range_sizek;
unsigned int reg;
unsigned long hole_startk, hole_sizek;
+ unsigned address_bits;
};
void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
@@ -300,47 +298,68 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
}
/* Write the range mtrrs */
if (state->range_sizek != 0) {
- if(state->hole_sizek == 0) {
- // we need to put that on to hole.
- unsigned long endk = basek + sizek;
+ if (state->hole_sizek == 0) {
+ /* We need to put that on to hole */
+ unsigned long endk = basek + sizek;
state->hole_startk = state->range_startk + state->range_sizek;
- state->hole_sizek = basek - state->hole_startk;
- state->range_sizek = endk - state->range_startk;
+ state->hole_sizek = basek - state->hole_startk;
+ state->range_sizek = endk - state->range_startk;
return;
}
- state->reg = range_to_mtrr(state->reg, state->range_startk, state->range_sizek, basek, MTRR_TYPE_WRBACK);
- state->reg = range_to_mtrr(state->reg, state->hole_startk, state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE);
+ state->reg = range_to_mtrr(state->reg, state->range_startk,
+ state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
+ state->reg = range_to_mtrr(state->reg, state->hole_startk,
+ state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
state->range_startk = 0;
state->range_sizek = 0;
state->hole_startk = 0;
state->hole_sizek = 0;
}
- /* Allocate an msr */
+ /* Allocate an msr */
+ printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
state->range_startk = basek;
state->range_sizek = sizek;
}
-void x86_setup_mtrrs(void)
+void x86_setup_fixed_mtrrs(void)
+{
+ /* Try this the simple way of incrementally adding together
+ * mtrrs. If this doesn't work out we can get smart again
+ * and clear out the mtrrs.
+ */
+ struct var_mtrr_state var_state;
+
+ printk_debug("\n");
+ /* Initialized the fixed_mtrrs to uncached */
+ printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
+ 0, NUM_FIXED_RANGES);
+ set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
+
+ /* Now see which of the fixed mtrrs cover ram.
+ */
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+ set_fixed_mtrr_resource, NULL);
+ printk_debug("DONE fixed MTRRs\n");
+
+ /* enable fixed MTRR */
+ printk_spew("call enable_fixed_mtrr()\n");
+ enable_fixed_mtrr();
+
+}
+void x86_setup_var_mtrrs(unsigned address_bits)
+/* this routine needs to know how many address bits a given processor
+ * supports. CPUs get grumpy when you set too many bits in
+ * their mtrr registers :( I would generically call cpuid here
+ * and find out how many physically supported but some cpus are
+ * buggy, and report more bits then they actually support.
+ */
{
/* Try this the simple way of incrementally adding together
* mtrrs. If this doesn't work out we can get smart again
* and clear out the mtrrs.
*/
struct var_mtrr_state var_state;
-#if !k8
- printk_debug("\n");
- /* Initialized the fixed_mtrrs to uncached */
- printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
- 0, NUM_FIXED_RANGES);
- set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
-
- /* Now see which of the fixed mtrrs cover ram.
- */
- search_global_resources(
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- set_fixed_mtrr_resource, NULL);
- printk_debug("DONE fixed MTRRs\n");
-#endif
/* Cache as many memory areas as possible */
/* FIXME is there an algorithm for computing the optimal set of mtrrs?
@@ -351,28 +370,35 @@ void x86_setup_mtrrs(void)
var_state.hole_startk = 0;
var_state.hole_sizek = 0;
var_state.reg = 0;
+ var_state.address_bits = address_bits;
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_var_mtrr_resource, &var_state);
/* Write the last range */
- var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, var_state.range_sizek, 0, MTRR_TYPE_WRBACK);
- var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE);
+ var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
+ var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
+ var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
+ var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
printk_debug("DONE variable MTRRs\n");
printk_debug("Clear out the extra MTRR's\n");
/* Clear out the extra MTRR's */
while(var_state.reg < MTRRS) {
- set_var_mtrr(var_state.reg++, 0, 0, 0);
+ set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
}
- /* enable fixed MTRR */
- printk_spew("call enable_fixed_mtrr()\n");
- enable_fixed_mtrr();
printk_spew("call enable_var_mtrr()\n");
enable_var_mtrr();
printk_spew("Leave %s\n", __FUNCTION__);
post_code(0x6A);
}
+void x86_setup_mtrrs(unsigned address_bits)
+{
+ x86_setup_fixed_mtrrs();
+ x86_setup_var_mtrrs(address_bits);
+}
+
+
int x86_mtrr_check(void)
{
/* Only Pentium Pro and later have MTRR */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 17:05:15 +0000