diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 13 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 13 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 12 |
5 files changed, 16 insertions, 35 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 024133b864..210d3566c7 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -324,8 +324,9 @@ no_msr_11e: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -340,7 +341,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -424,11 +425,7 @@ before_romstage: __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 276b9c3a63..f0d49390ba 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -177,7 +177,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. It also contains the information * for setting up MTRRs. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -225,9 +225,6 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - /* Get number of MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 29ff01a26a..93d690748f 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -156,8 +156,8 @@ clear_var_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer below the end of CAR. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ @@ -169,11 +169,10 @@ before_romstage: post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -272,11 +271,7 @@ before_romstage: __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index cc52637076..d51fd01c05 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -178,7 +178,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -285,11 +285,7 @@ before_romstage: __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index b4c8d62b63..1673242884 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -125,8 +125,8 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ @@ -142,7 +142,7 @@ before_romstage: /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -226,11 +226,7 @@ before_romstage: __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) |