diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/agesa/heapmanager.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 8 |
2 files changed, 4 insertions, 10 deletions
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 50ec3ffc51..cc53d35662 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -12,13 +12,11 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) + if (acpi_is_wakeup_s3()) heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ -#endif + return heap; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 8bc5cd3320..6c320906ae 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -101,12 +101,10 @@ void post_cache_as_ram(void) { void *resume_backup_memory = NULL; - int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early(); + int s3resume = acpi_is_wakeup_s3(); if (s3resume) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) cbmem_recovery(s3resume); resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_romstage_ramstack(resume_backup_memory); @@ -141,10 +139,8 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_s3_resume_allowed() && acpi_is_wakeup_early()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (acpi_is_wakeup_s3()) { resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_ramstage_region(resume_backup_memory); |