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-rw-r--r--src/cpu/amd/agesa/Kconfig2
-rw-r--r--src/cpu/amd/agesa/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family15rl/Kconfig39
-rw-r--r--src/cpu/amd/agesa/family15rl/Makefile.inc32
-rw-r--r--src/cpu/amd/agesa/family15rl/acpi/cpu.asl78
-rw-r--r--src/cpu/amd/agesa/family15rl/chip_name.c21
-rw-r--r--src/cpu/amd/agesa/family15rl/fixme.c81
-rw-r--r--src/cpu/amd/agesa/family15rl/model_15_init.c140
-rw-r--r--src/cpu/amd/agesa/family15rl/romstage.c61
-rw-r--r--src/cpu/amd/agesa/family15rl/udelay.c58
-rw-r--r--src/cpu/x86/smm/smmhandler.S3
11 files changed, 1 insertions, 515 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 15bd64324b..95db82f982 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -19,7 +19,6 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15
default y if CPU_AMD_AGESA_FAMILY15_TN
- default y if CPU_AMD_AGESA_FAMILY15_RL
default y if CPU_AMD_AGESA_FAMILY16_KB
default n
select ARCH_BOOTBLOCK_X86_32
@@ -85,5 +84,4 @@ source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
-source src/cpu/amd/agesa/family15rl/Kconfig
source src/cpu/amd/agesa/family16kb/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index f6a3e67675..1d5e705277 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -16,7 +16,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig
deleted file mode 100644
index 85087ef128..0000000000
--- a/src/cpu/amd/agesa/family15rl/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-config CPU_AMD_AGESA_FAMILY15_RL
- bool
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY15_RL
-
-config CPU_ADDR_BITS
- int
- default 48
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x100000
-
-endif # CPU_AMD_AGESA_FAMILY15_RL
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc
deleted file mode 100644
index 4fcaff7405..0000000000
--- a/src/cpu/amd/agesa/family15rl/Makefile.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../smm
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/family15rl/acpi/cpu.asl b/src/cpu/amd/agesa/family15rl/acpi/cpu.asl
deleted file mode 100644
index 88d611e9ac..0000000000
--- a/src/cpu/amd/agesa/family15rl/acpi/cpu.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- /*
- * Processor Object
- *
- */
- Scope (\_PR) { /* define processor scope */
- Processor(
- P000, /* name space name */
- 0, /* Unique number for this processor */
- 0x810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
-
- Processor(
- P001, /* name space name */
- 1, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P002, /* name space name */
- 2, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P003, /* name space name */
- 3, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P004, /* name space name */
- 4, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P005, /* name space name */
- 5, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P006, /* name space name */
- 6, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- Processor(
- P007, /* name space name */
- 7, /* Unique number for this processor */
- 0x0810, /* PBLK system I/O address !hardcoded! */
- 0x06 /* PBLKLEN for boot processor */
- ) {
- }
- } /* End _PR scope */
diff --git a/src/cpu/amd/agesa/family15rl/chip_name.c b/src/cpu/amd/agesa/family15rl/chip_name.c
deleted file mode 100644
index cd4a0d83aa..0000000000
--- a/src/cpu/amd/agesa/family15rl/chip_name.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family15rl_ops = {
- CHIP_NAME("AMD CPU Family 15h Model 10h-1Fh")
-};
diff --git a/src/cpu/amd/agesa/family15rl/fixme.c b/src/cpu/amd/agesa/family15rl/fixme.c
deleted file mode 100644
index 2eb96891a0..0000000000
--- a/src/cpu/amd/agesa/family15rl/fixme.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include "amdlib.h"
-
-void amd_initcpuio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
- * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
- * set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
- PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
- PciData |= 1 << 7; /* set NP (non-posted) bit */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
- PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
- PciData = 0x00FECF00; /* last address before non-posted range */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
- PciData = 0x0000F000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
-
-void amd_initmmio(void)
-{
- UINT64 MsrReg;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-}
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c
deleted file mode 100644
index 6d2bec2404..0000000000
--- a/src/cpu/amd/agesa/family15rl/model_15_init.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/pae.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
-#include <arch/acpi.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
-static void model_15_init(device_t dev)
-{
- printk(BIOS_DEBUG, "Model 15 Init.\n");
-
- u8 i;
- msr_t msr;
- int msrno;
- unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- u32 siblings;
-#endif
-
- //x86_enable_cache();
- amd_setup_mtrrs();
- //x86_mtrr_check();
- disable_cache ();
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
- msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
- msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
- wrmsr (msrno, msr);
-
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- if (acpi_is_wakeup())
- restore_mtrr();
-
- x86_mtrr_check();
- x86_enable_cache();
-
- /* zero the machine check error status registers */
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < 6; i++) {
- wrmsr(MCI_STATUS + (i * 4), msr);
- }
-
- /* Enable the local CPU APICs */
- setup_lapic();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- cpu_idx = cpu_info()->index;
- printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
-
- /* Set SMM base address for this CPU */
- msr = rdmsr(MSR_SMM_BASE);
- msr.lo = SMM_BASE - (cpu_idx * 0x400);
- wrmsr(MSR_SMM_BASE, msr);
-
- /* Enable the SMM memory window */
- msr = rdmsr(MSR_SMM_MASK);
- msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
- wrmsr(MSR_SMM_MASK, msr);
- }
-
- /* Write protect SMM space with SMMLOCK. */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_15_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
- { 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
deleted file mode 100644
index 5c7d972692..0000000000
--- a/src/cpu/amd/agesa/family15rl/romstage.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/amd/car.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- if (!cb->s3resume) {
- printk(BIOS_INFO, "Normal boot\n");
-
- post_code(0x40);
- agesawrapper_amdinitpost();
- } else {
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
- }
-
-}
-void agesa_postcar(struct sysinfo *cb)
-{
- if (!cb->s3resume) {
- printk(BIOS_INFO, "Normal boot postcar\n");
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- } else {
- printk(BIOS_INFO, "S3 resume postcar\n");
-
- post_code(0x61);
- amd_initcpuio();
-
- post_code(0x62);
- agesawrapper_amds3laterestore();
- }
-}
diff --git a/src/cpu/amd/agesa/family15rl/udelay.c b/src/cpu/amd/agesa/family15rl/udelay.c
deleted file mode 100644
index 272e103110..0000000000
--- a/src/cpu/amd/agesa/family15rl/udelay.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * udelay() impementation for SMI handlers
- * This is neat in that it never writes to hardware registers, and thus does not
- * modify the state of the hardware while servicing SMIs.
- */
-
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <delay.h>
-#include <stdint.h>
-
-void udelay(uint32_t us)
-{
- uint8_t fid, did, pstate_idx;
- uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
- msr_t msr;
- const uint64_t tsc_base = 100000000;
-
- /* Get initial timestamp before we do the math */
- tsc_start = rdtscll();
-
- /* Get the P-state. This determines which MSR to read */
- msr = rdmsr(0xc0010063);
- pstate_idx = msr.lo & 0x07;
-
- /* Get FID and VID for current P-State */
- msr = rdmsr(0xc0010064 + pstate_idx);
-
- /* Extract the FID and VID values */
- fid = msr.lo & 0x3f;
- did = (msr.lo >> 6) & 0x7;
-
- /* Calculate the CPU clock (from base freq of 100MHz) */
- tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
-
- /* Now go on and wait */
- tsc_wait_ticks = (tsc_clock / 1000000) * us;
-
- do {
- tsc_now = rdtscll();
- } while (tsc_now - tsc_wait_ticks < tsc_start);
-}
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index b57d015789..98d67d3c3c 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -141,8 +141,7 @@ untampered_lapic:
/* This is an ugly hack, and we should find a way to read the CPU index
* without relying on the LAPIC ID.
*/
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) \
- || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
/* LAPIC IDs start from 0x10; map that to the proper core index */
subl $0x10, %ecx
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 17:29:12 +0000