8 files changed, 79 insertions, 0 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index f60ffe7cce..caf4ebc1b6 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -3,6 +3,7 @@
 # (See also src/Kconfig)
 if ARCH_ARMV7
 
+source src/cpu/armltd/Kconfig
 source src/cpu/samsung/Kconfig
 
 endif	# ARCH_ARM
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 93b16ae3bd..e1efecc7f5 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -2,6 +2,7 @@
 ## Subdirectories
 ################################################################################
 subdirs-y += amd
+subdirs-y += armltd
 subdirs-y += intel
 subdirs-y += samsung
 subdirs-y += via
diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig
new file mode 100644
index 0000000000..b1f4c2ee4e
--- /dev/null
+++ b/src/cpu/armltd/Kconfig
@@ -0,0 +1,8 @@
+config CPU_ARMLTD_CORTEX_A9
+	depends on ARCH_ARMV7
+	bool
+	default n
+
+if CPU_ARMLTD_CORTEX_A9
+source src/cpu/armltd/cortex-a9/Kconfig
+endif
diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc
new file mode 100644
index 0000000000..014742f056
--- /dev/null
+++ b/src/cpu/armltd/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9
diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig
new file mode 100644
index 0000000000..7f35cfd653
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/Kconfig
@@ -0,0 +1,5 @@
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/armltd/cortex-a9/bootblock.c"
+	help
+	  CPU/SoC-specific bootblock code.
diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc
new file mode 100644
index 0000000000..d1e7edfdee
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cache.c
+romstage-y += cache.c
diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c
new file mode 100644
index 0000000000..8925439d2a
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/bootblock.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+void bootblock_cpu_init(void);
+void bootblock_cpu_init(void)
+{
+}
diff --git a/src/cpu/armltd/cortex-a9/cache.c b/src/cpu/armltd/cortex-a9/cache.c
new file mode 100644
index 0000000000..957871dba7
--- /dev/null
+++ b/src/cpu/armltd/cortex-a9/cache.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <system.h>
+#include <armv7.h>
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+}
+
+/* stubs so we don't need weak symbols in cache_v7.c */
+void v7_outer_cache_disable(void)
+{
+}
+
+void v7_outer_cache_flush_all(void)
+{
+}
+
+void v7_outer_cache_inval_all(void)
+{
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+}