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-rw-r--r--src/cpu/x86/Kconfig4
-rw-r--r--src/cpu/x86/lapic/Makefile.inc1
-rw-r--r--src/cpu/x86/lapic/boot_cpu.c3
-rw-r--r--src/cpu/x86/mtrr/mtrr.c14
4 files changed, 19 insertions, 3 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index d2809f8fe8..68946227b9 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -40,4 +40,6 @@ config LOGICAL_CPUS
bool
default y
-
+config CACHE_ROM
+ bool
+ default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956a9a..f3fcadc0a7 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0883..0fb9d5d35c 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
{
int bsp;
msr_t msr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d4c7..9015ad4d97 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <arch/acpi.h>
#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
};
-
void enable_fixed_mtrr(void)
{
msr_t msr;
@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
while(var_state.reg < MTRRS) {
set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
}
+
+#if CONFIG_CACHE_ROM
+ /* Enable Caching and speculative Reads for the
+ * complete ROM now that we actually have RAM.
+ */
+ if (boot_cpu() && (acpi_slp_type != 3)) {
+ set_var_mtrr(7, (4096-4)*1024, 4*1024,
+ MTRR_TYPE_WRPROT, address_bits);
+ }
+#endif
+
printk(BIOS_SPEW, "call enable_var_mtrr()\n");
enable_var_mtrr();
printk(BIOS_SPEW, "Leave %s\n", __func__);