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-rw-r--r--src/cpu/intel/haswell/romstage.c10
1 files changed, 2 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index d9098373cd..8c65dae237 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -18,6 +18,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <arch/cpu.h>
+#include <cf9_reset.h>
#include <cpu/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
@@ -32,7 +33,6 @@
#include <cbmem.h>
#include <program_loading.h>
#include <romstage_handoff.h>
-#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
@@ -44,12 +44,6 @@
#include <cpu/intel/romstage.h>
#include "haswell.h"
-static inline void reset_system(void)
-{
- hard_reset();
- halt();
-}
-
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* platform_enter_postcar() determines the stack to use after
@@ -147,7 +141,7 @@ void romstage_common(const struct romstage_params *params)
} else if (cbmem_initialize()) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
/* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ system_reset();
#endif
}