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-rw-r--r--src/cpu/intel/model_f0x/Kconfig1
-rw-r--r--src/cpu/intel/model_f1x/Kconfig1
-rw-r--r--src/cpu/intel/model_f2x/Kconfig1
-rw-r--r--src/cpu/intel/model_f3x/Kconfig1
-rw-r--r--src/cpu/intel/model_f4x/Kconfig1
-rw-r--r--src/cpu/intel/socket_mPGA604/Kconfig8
6 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig
index bf26cfe048..9dd7fd0bdc 100644
--- a/src/cpu/intel/model_f0x/Kconfig
+++ b/src/cpu/intel/model_f0x/Kconfig
@@ -1,4 +1,3 @@
config CPU_INTEL_MODEL_F0X
bool
select SMP
- select SSE2
diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig
index 328930cb8c..ea75857949 100644
--- a/src/cpu/intel/model_f1x/Kconfig
+++ b/src/cpu/intel/model_f1x/Kconfig
@@ -1,4 +1,3 @@
config CPU_INTEL_MODEL_F1X
bool
select SMP
- select SSE2
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 1672fda7e9..50cac7937c 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -1,4 +1,3 @@
config CPU_INTEL_MODEL_F2X
bool
select SMP
- select SSE2
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index 1a2fa36922..4cfca83dc6 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -1,4 +1,3 @@
config CPU_INTEL_MODEL_F3X
bool
select SMP
- select SSE2
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index e765e335d6..97c909a0ae 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -1,4 +1,3 @@
config CPU_INTEL_MODEL_F4X
bool
select SMP
- select SSE2
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 2668174e71..faa74d3390 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -6,3 +6,11 @@ config CPU_INTEL_SOCKET_MPGA604
select MMX
select SSE
select UDELAY_TSC
+
+# mPGA604 are usually Intel Netburst CPUs which should have SSE2
+# but the ramtest.c code on the Dell S1850 seems to choke on
+# enabling it, so disable it for now.
+config SSE2
+ bool
+ default n
+ depends on CPU_INTEL_SOCKET_MPGA604