diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/apic_timer.c | 59 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/apic_timer.c | 55 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/apic_timer.c | 29 | ||||
| -rw-r--r-- | src/cpu/x86/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 13 |
12 files changed, 31 insertions, 147 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 39175fc79e..d57bded604 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default n select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_AGESA @@ -44,6 +45,10 @@ config XIP_ROM_SIZE In order to execute romstage in place on the flash rom, more space is required to be set as write through caching. +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 6c6cb89eda..401be3e532 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,5 +24,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c deleted file mode 100644 index ec6ddd5473..0000000000 --- a/src/cpu/amd/agesa/apic_timer.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 0254cf239c..c5bdb4a5f8 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_MODEL_10XXX select SSE2 select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS @@ -56,6 +57,10 @@ config SET_FIDVID_CORE_RANGE endif # SET_FIDVID +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + config UPDATE_CPU_MICROCODE bool default y diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index c9becbdb6e..81c565b621 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,4 +1,3 @@ ramstage-y += model_10xxx_init.c ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c -ramstage-y += apic_timer.c ramstage-y += processor_name.c diff --git a/src/cpu/amd/model_10xxx/apic_timer.c b/src/cpu/amd/model_10xxx/apic_timer.c deleted file mode 100644 index d961da795b..0000000000 --- a/src/cpu/amd/model_10xxx/apic_timer.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 28beacfa45..fb094b1a5d 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_MODEL_FXX select SSE select SSE2 select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_MODEL_FXX config UDELAY_IO @@ -23,6 +24,10 @@ config HW_SCRUBBER bool default n +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + if SET_FIDVID config SET_FIDVID_DEBUG bool diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 99c09c8395..e016235f7e 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,6 +1,5 @@ # no conditionals here. If you include this file from a socket, then you get all the binaries. ramstage-y += model_fxx_init.c -ramstage-y += apic_timer.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c deleted file mode 100644 index 6eb99a4eba..0000000000 --- a/src/cpu/amd/model_fxx/apic_timer.c +++ /dev/null @@ -1,29 +0,0 @@ -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - -void udelay(unsigned usecs) -{ - uint32_t start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4300c3d0e4..ae3241e8b3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -11,6 +11,9 @@ config UDELAY_LAPIC bool default n +config UDELAY_LAPIC_FIXED_FSB + int + config UDELAY_TSC bool default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index f3fcadc0a7..6663c12880 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 562c79c2e8..53209fbbff 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,7 +20,9 @@ #include <stdint.h> #include <delay.h> +#include <arch/io.h> #include <arch/cpu.h> +#include <cpu/x86/car.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> @@ -28,7 +30,15 @@ * memory init. */ -static u32 timer_fsb = 0; +#if CONFIG_UDELAY_LAPIC_FIXED_FSB +static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB; + +static int set_timer_fsb(void) +{ + return 0; +} +#else +static u32 timer_fsb CAR_GLOBAL = 0; static int set_timer_fsb(void) { @@ -60,6 +70,7 @@ static int set_timer_fsb(void) return 0; } +#endif void init_timer(void) { |