diff options
Diffstat (limited to 'src/drivers/intel/fsp1_1/stage_cache.c')
-rw-r--r-- | src/drivers/intel/fsp1_1/stage_cache.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c new file mode 100644 index 0000000000..5ad24c03bd --- /dev/null +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <fsp/memmap.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} |