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-rw-r--r--src/drivers/intel/gma/i915.h24
-rw-r--r--src/drivers/intel/gma/i915_reg.h1
-rw-r--r--src/drivers/intel/gma/intel_ddi.c66
3 files changed, 91 insertions, 0 deletions
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 62fe0230e6..1aed2bfb09 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -40,6 +40,22 @@
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
+enum port {
+ PORT_A = 0,
+ PORT_B,
+ PORT_C,
+ PORT_D,
+ PORT_E,
+ I915_NUM_PORTS
+};
+
+enum pipe {
+ PIPE_A = 0,
+ PIPE_B,
+ PIPE_C,
+ I915_NUM_PIPES
+};
+
/* debug enums. These are for printks that, due to their place in the
* middle of graphics device IO, might change timing. Use with care
* or not at all.
@@ -143,6 +159,7 @@ struct intel_dp {
u32 pipesrc;
u32 stride;
struct intel_dp_m_n m_n;
+ u32 flags;
};
/* we may yet need these. */
@@ -197,3 +214,10 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
unsigned int pixel_clock,
unsigned int link_clock,
struct intel_dp_m_n *m_n);
+
+u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
+ enum port port,
+ enum pipe pipe,
+ int type,
+ int lane_count,
+ int pf_sz);
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index 27a3d2b7da..d0c8c85f94 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -4554,6 +4554,7 @@
#define DDI_BUF_EMP_MASK (0xf<<24)
#define DDI_BUF_IS_IDLE (1<<7)
#define DDI_A_4_LANES (1<<4)
+#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
#define DDI_PORT_WIDTH_X1 (0<<1)
#define DDI_PORT_WIDTH_X2 (1<<1)
#define DDI_PORT_WIDTH_X4 (3<<1)
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 220bd47100..f1a40f1e32 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -157,3 +157,69 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port)
udelay(600);
}
+
+u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
+ enum port port,
+ enum pipe pipe,
+ int type,
+ int lane_count,
+ int pf_sz)
+{
+ u32 temp;
+
+ temp = TRANS_DDI_FUNC_ENABLE;
+ temp |= TRANS_DDI_SELECT_PORT(port);
+
+ switch (pipe_bpp) {
+ case 18:
+ temp |= TRANS_DDI_BPC_6;
+ break;
+ case 24:
+ temp |= TRANS_DDI_BPC_8;
+ break;
+ case 30:
+ temp |= TRANS_DDI_BPC_10;
+ break;
+ case 36:
+ temp |= TRANS_DDI_BPC_12;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed *** \n", pipe_bpp);
+ }
+
+ if (port == PORT_A) {
+ switch (pipe) {
+ case PIPE_A:
+ if (pf_sz)
+ temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
+ else
+ temp |= TRANS_DDI_EDP_INPUT_A_ON;
+ break;
+ case PIPE_B:
+ temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+ break;
+ case PIPE_C:
+ temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid pipe %d\n", pipe);
+ }
+ }
+
+ /* We need to check for TRANS_DDI_PVSYNC and TRANS_DDI_PHSYNC -- How? */
+
+ if (type == INTEL_OUTPUT_HDMI) {
+ /* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */
+ } else if (type == INTEL_OUTPUT_ANALOG) {
+ /* Set TRANS_DDI_MODE_SELECT_FDI with lane_count */
+ } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
+ type == INTEL_OUTPUT_EDP) {
+ temp |= TRANS_DDI_MODE_SELECT_DP_SST;
+
+ temp |= DDI_PORT_WIDTH(lane_count);
+ } else {
+ printk(BIOS_ERR, "Invalid type %d for pipe\n", type);
+ }
+
+ return temp;
+}