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-rw-r--r--src/drivers/intel/fsp1_1/after_raminit.S13
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h7
2 files changed, 20 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index eb99157959..122c0bf03e 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -87,6 +87,13 @@
* +0: Number of variable MTRRs to clear
*/
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ push %esp
+ call soc_set_mtrrs
+
+ /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
+ movl %eax, %esp
+#else
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
@@ -129,6 +136,8 @@
dec %ebx
jmp 2b
2:
+#endif /* CONFIG_SOC_SETS_MTRRS */
+
post_code(0x39)
/* And enable cache again after setting MTRRs. */
@@ -138,11 +147,15 @@
post_code(0x3a)
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ call soc_enable_mtrrs
+#else
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
+#endif /* CONFIG_SOC_SETS_MTRRS */
post_code(0x3b)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 4683f5e5a2..d07dc375c8 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -88,4 +88,11 @@ void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd);
void soc_pre_ram_init(struct romstage_params *params);
+/*
+ * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
+ * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.
+ */
+asmlinkage void *soc_set_mtrrs(void *top_of_stack);
+asmlinkage void soc_enable_mtrrs(void);
+
#endif /* _COMMON_ROMSTAGE_H_ */