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-rw-r--r--src/drivers/uart/Makefile.inc12
-rw-r--r--src/drivers/uart/uart8250io.c131
-rw-r--r--src/drivers/uart/uart8250mem.c133
-rw-r--r--src/drivers/uart/uart8250reg.h108
4 files changed, 384 insertions, 0 deletions
diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc
index 52a7024318..3a9ca3d592 100644
--- a/src/drivers/uart/Makefile.inc
+++ b/src/drivers/uart/Makefile.inc
@@ -5,6 +5,18 @@ bootblock-y += util.c
smm-y += util.c
endif
+ifeq ($(CONFIG_CONSOLE_SERIAL8250),y)
+romstage-y += uart8250io.c
+ramstage-y += uart8250io.c
+smm-y += uart8250io.c
+endif
+
+ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
+romstage-y += uart8250mem.c
+ramstage-y += uart8250mem.c
+smm-y += uart8250mem.c
+endif
+
ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
ifeq ($(CONFIG_DRIVERS_UART_PL011),y)
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
new file mode 100644
index 0000000000..e4e8b6cfd7
--- /dev/null
+++ b/src/drivers/uart/uart8250io.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/uart.h>
+#include <trace.h>
+#include "uart8250reg.h"
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Nominal values only, good for the range of choices Kconfig offers for
+ * set of standard baudrates.
+ */
+#define BAUDRATE_REFCLK (115200)
+#define BAUDRATE_OVERSAMPLE (1)
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ *
+ * Estimated that inb() from UART takes 1 microsecond.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+
+static int uart8250_can_tx_byte(unsigned base_port)
+{
+ return inb(base_port + UART_LSR) & UART_LSR_THRE;
+}
+
+static void uart8250_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_can_tx_byte(base_port));
+ outb(data, base_port + UART_TBR);
+}
+
+static void uart8250_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
+}
+
+static int uart8250_can_rx_byte(unsigned base_port)
+{
+ return inb(base_port + UART_LSR) & UART_LSR_DR;
+}
+
+static unsigned char uart8250_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_can_rx_byte(base_port));
+
+ if (i)
+ return inb(base_port + UART_RBR);
+ else
+ return 0x0;
+}
+
+static void uart8250_init(unsigned base_port, unsigned divisor)
+{
+ DISABLE_TRACE;
+ /* Disable interrupts */
+ outb(0x0, base_port + UART_IER);
+ /* Enable FIFOs */
+ outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
+
+ /* assert DTR and RTS so the other end is happy */
+ outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
+
+ /* DLAB on */
+ outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
+
+ /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
+ outb(divisor & 0xFF, base_port + UART_DLL);
+ outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
+
+ /* Set to 3 for 8N1 */
+ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+ ENABLE_TRACE;
+}
+
+/* FIXME: Needs uart index from Kconfig.
+ * Already use array as a work-around for ROMCC.
+ */
+static const unsigned bases[1] = { CONFIG_TTYS0_BASE };
+
+void uart_init(void)
+{
+ unsigned int div;
+ div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
+ BAUDRATE_OVERSAMPLE);
+ uart8250_init(bases[0], div);
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ uart8250_tx_byte(bases[0], data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+ return uart8250_rx_byte(bases[0]);
+}
+
+int uart_can_rx_byte(void)
+{
+ return uart8250_can_rx_byte(bases[0]);
+}
+
+void uart_tx_flush(void)
+{
+ uart8250_tx_flush(bases[0]);
+}
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
new file mode 100644
index 0000000000..74929f5923
--- /dev/null
+++ b/src/drivers/uart/uart8250mem.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/uart.h>
+#include <device/device.h>
+#include <delay.h>
+#include "uart8250reg.h"
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+ return read8(base_port + UART_LSR) & UART_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while(i-- && !uart8250_mem_can_tx_byte(base_port))
+ udelay(1);
+ write8(base_port + UART_TBR, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
+ udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+ return read8(base_port + UART_LSR) & UART_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while(i-- && !uart8250_mem_can_rx_byte(base_port))
+ udelay(1);
+ if (i)
+ return read8(base_port + UART_RBR);
+ else
+ return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+ /* Disable interrupts */
+ write8(base_port + UART_IER, 0x0);
+ /* Enable FIFOs */
+ write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
+
+ /* Assert DTR and RTS so the other end is happy */
+ write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
+
+ /* DLAB on */
+ write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+ write8(base_port + UART_DLL, divisor & 0xFF);
+ write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
+
+ /* Set to 3 for 8N1 */
+ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
+}
+
+void uart_init(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+
+ unsigned int div;
+ div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
+ uart8250_mem_init(base, div);
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_byte(base, data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return 0xff;
+ return uart8250_mem_rx_byte(base);
+}
+
+int uart_can_rx_byte(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return 0;
+ return uart8250_mem_can_rx_byte(base);
+}
+
+void uart_tx_flush(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_flush(base);
+}
diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h
new file mode 100644
index 0000000000..cdfbb1bc20
--- /dev/null
+++ b/src/drivers/uart/uart8250reg.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef UART8250REG_H
+#define UART8250REG_H
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+#define UART_IIR 0x02
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+#define UART_FCR 0x02
+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+#define UART_LCR 0x03
+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define UART_LCR_PEN 0x08 /* Parity enable */
+#define UART_LCR_EPS 0x10 /* Even Parity Select */
+#define UART_LCR_STKP 0x20 /* Stick Parity */
+#define UART_LCR_SBRK 0x40 /* Set Break */
+#define UART_LCR_BKSE 0x80 /* Bank select enable */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+#define UART_MCR 0x04
+#define UART_MCR_DTR 0x01 /* DTR */
+#define UART_MCR_RTS 0x02 /* RTS */
+#define UART_MCR_OUT1 0x04 /* Out 1 */
+#define UART_MCR_OUT2 0x08 /* Out 2 */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+
+#define UART_MCR_DMA_EN 0x04
+#define UART_MCR_TX_DFR 0x08
+
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_LSR_DR 0x01 /* Data ready */
+#define UART_LSR_OE 0x02 /* Overrun */
+#define UART_LSR_PE 0x04 /* Parity error */
+#define UART_LSR_FE 0x08 /* Framing error */
+#define UART_LSR_BI 0x10 /* Break */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
+#define UART_LSR_ERR 0x80 /* Error */
+
+#define UART_MSR 0x06
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+
+#define UART_SCR 0x07
+#define UART_SPR 0x07
+
+#endif /* UART8250REG_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 12:55:20 +0000