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-rw-r--r--src/drivers/intel/gma/Kconfig7
-rw-r--r--src/drivers/intel/gma/opregion.c14
-rw-r--r--src/drivers/intel/gma/opregion.h1
3 files changed, 20 insertions, 2 deletions
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index a4b8a4a161..9e2872bb6c 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -47,6 +47,13 @@ config INTEL_GMA_SSC_ALTERNATE_REF
supported platform with a choice seems to be Pineview, where the
alternative is 100MHz vs. the default 96MHz.
+config INTEL_GMA_SWSMISCI
+ bool
+ default n
+ help
+ Select this option for Atom-based platforms which use the SWSMISCI
+ register (0xe0) rather than the SWSCI register (0xe8).
+
config GFX_GMA_ANALOG_I2C_HDMI_B
bool
diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index 74c629c9c2..b939b88324 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -32,6 +32,7 @@ void intel_gma_opregion_register(uintptr_t opregion)
{
device_t igd;
u16 reg16;
+ u16 sci_reg;
igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
if (!igd || !igd->enabled)
@@ -44,14 +45,23 @@ void intel_gma_opregion_register(uintptr_t opregion)
pci_write_config32(igd, ASLS, opregion);
/*
+ * Atom-based platforms use a combined SMI/SCI register,
+ * whereas non-Atom platforms use a separate SCI register.
+ */
+ if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
+ sci_reg = SWSMISCI;
+ else
+ sci_reg = SWSCI;
+
+ /*
* Intel's Windows driver relies on this:
* Intel BIOS Specification
* Chapter 5.4 "ASL Software SCI Handler"
*/
- reg16 = pci_read_config16(igd, SWSCI);
+ reg16 = pci_read_config16(igd, sci_reg);
reg16 &= ~GSSCIE;
reg16 |= SMISCISEL;
- pci_write_config16(igd, SWSCI, reg16);
+ pci_write_config16(igd, sci_reg, reg16);
}
/* Restore ASLS register on S3 resume and prepare SWSCI. */
diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index 3ae68e527b..8ef3dcf9be 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -25,6 +25,7 @@
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
#define SWSCI 0xe8 /* SWSCI Register */
+#define SWSMISCI 0xe0 /* SWSMISCI Register */
#define GSSCIE (1 << 0) /* SCI Event trigger */
#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */