diff options
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/em64t100_save_state.h | 106 | ||||
| -rw-r--r-- | src/include/cpu/intel/em64t101_save_state.h | 120 | ||||
| -rw-r--r-- | src/include/cpu/intel/em64t_save_state.h | 101 |
3 files changed, 327 insertions, 0 deletions
diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h new file mode 100644 index 0000000000..f76fa4badd --- /dev/null +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T100_SAVE_STATE_H__ +#define __EM64T100_SAVE_STATE_H__ + +#include <types.h> +#include <cpu/x86/smm.h> + +/* Intel Revision 30100 SMM State-Save Area + * The following processor architectures use this: + * - Bay Trail + */ +#define SMM_EM64T100_ARCH_OFFSET 0x7c00 +#define SMM_EM64T100_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved2[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + + u8 reserved3[64]; + u32 cr4; + + u8 reserved4[72]; + + u32 gdtr_base; + u8 reserved5[4]; + u32 idtr_base; + u8 reserved6[4]; + u32 ldtr_base; + + u8 reserved7[88]; + + u32 smbase; + u32 smm_revision; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved8[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t100_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h new file mode 100644 index 0000000000..b8bb2db58f --- /dev/null +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T101_SAVE_STATE_H__ +#define __EM64T101_SAVE_STATE_H__ + +#include <types.h> +#include <cpu/x86/smm.h> + + +/* Intel Revision 30101 SMM State-Save Area + * The following processor architectures use this: + * - SandyBridge + * - IvyBridge + * - Haswell + */ +#define SMM_EM64T101_ARCH_OFFSET 0x7c00 +#define SMM_EM64T101_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u32 io_cf8; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + + u8 reserved2[52]; + u32 shutdown_auto_restart; + u8 reserved3[8]; + u32 cr4; + + u8 reserved4[72]; + + u32 gdtr_base; + u8 reserved5[4]; + u32 idtr_base; + u8 reserved6[4]; + u32 ldtr_base; + + u8 reserved7[56]; + /* EPTP fields are only on Haswell according to BWGs, but Intel was + * wise and reused the same revision number. */ + u64 eptp; + u32 eptp_en; + u32 cs_base; + u8 reserved8[4]; + u32 iedbase; + + u8 reserved9[8]; + + u32 smbase; + u32 smm_revision; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved10[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t101_smm_state_save_area_t; + +#endif diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h new file mode 100644 index 0000000000..1dd01a61a4 --- /dev/null +++ b/src/include/cpu/intel/em64t_save_state.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __EM64T_SAVE_STATE_H__ +#define __EM64T_SAVE_STATE_H__ + +#include <types.h> +#include <cpu/x86/smm.h> + +/* Intel Core 2 (EM64T) SMM State-Save Area + * starts @ 0x7c00 + */ +#define SMM_EM64T_ARCH_OFFSET 0x7c00 +#define SMM_EM64T_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET) +typedef struct { + u8 reserved0[256]; + u8 reserved1[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved2[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + u64 cr4; + + u8 reserved3[68]; + + u64 gdtr_base; + u64 idtr_base; + u64 ldtr_base; + + u8 reserved4[84]; + + u32 smm_revision; + u32 smbase; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved5[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __packed em64t_smm_state_save_area_t; + +#endif |