summaryrefslogtreecommitdiff
path: root/src/include/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/gx2def.h8
-rw-r--r--src/include/cpu/amd/lxdef.h2
-rw-r--r--src/include/cpu/amd/sc520.h6
3 files changed, 8 insertions, 8 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index beb4c65483..60db369cf3 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -78,7 +78,7 @@
#define GL1_PCI 4
#define GL1_FG 5
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
@@ -86,9 +86,9 @@
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
#define MSR_DF (GL0_DF << 29) /* C000xxxx */
-#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
-#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
-#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
+#define MSR_FG ((GL1_FG << 26) + MSR_GLIU1) /* 5400xxxx */
/* GeodeLink Interface Unit 0 (GLIU0) port0 */
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 19b1efa3d6..4865bea2ed 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -59,7 +59,7 @@
#define GL1_AES 6
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
+#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
diff --git a/src/include/cpu/amd/sc520.h b/src/include/cpu/amd/sc520.h
index 53a62b5880..4e748be530 100644
--- a/src/include/cpu/amd/sc520.h
+++ b/src/include/cpu/amd/sc520.h
@@ -10,11 +10,11 @@ struct parreg {
unsigned long reg[16];
};
-#define PARREG (struct parreg *)0xfffef088
+#define PARREG ((struct parreg *)0xfffef088)
//static volatile struct parreg *par = PARREG;
-#define MMCRPIC (struct mmcrpic *) 0xfffefd00
+#define MMCRPIC ((struct mmcrpic *) 0xfffefd00)
//static volatile struct mmcrpic *pic = MMCRPIC;
#define M_GINT_MODE 1
@@ -308,4 +308,4 @@ struct mmcr {
};
-#define MMCRDEFAULT (struct mmcr *) 0xfffef000
+#define MMCRDEFAULT ((struct mmcr *) 0xfffef000)